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UPSD3312D Datasheet(PDF) 145 Page - STMicroelectronics

Part # UPSD3312D
Description  fast 8032 MCU with programmable logic
PDF  272 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3312D Datasheet(HTML) 145 Page - STMicroelectronics

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UPSD33xx
Synchronous peripheral interface (SPI)
Doc ID 9685 Rev 7
145/272
24.4
SPI SFR registers
Six SFR registers control the SPI interface:
●
SPICON0 (Table 85 on page 147) for interface control
●
SPICON1 (Table 87 on page 148) for interrupt control
●
SPITDR (SFR D4h, Write only) holds byte to transmit
●
SPIRDR (SFR D5h, Read only) holds byte received
●
SPICLKD (Table 89 on page 148) for clock divider
●
SPISTAT (Table 91 on page 149) holds interface status
The SPI interface functional block diagram (Figure 44 on page 145) shows these six SFRs.
Both the transmit and receive data paths are double-buffered, meaning that continuous
transmitting or receiving (back-to-back transfer) is possible by reading from SPIRDR or
writing data to SPITDR while shifting is taking place. There are a number of flags in the
SPISTAT register that indicate when it is full or empty to assist the 8032 MCU in data flow
management. When enabled, these status flags will cause an interrupt to the MCU.
Figure 44.
SPI Interface, Master mode only
SPITDR - TRANSMIT REGISTER
SPITxD / P1.6 or P4.6
TIMING AND CONTROL
(fOSC)
INTR
to
8032
SPIRDR - RECEIVE REGISTER
8-bit SHIFT REGISTER
8
8
8
8
SPIRxD /
P1.5 or P4.5
SPICON0, SPICON1
- CONTROL REGISTERS
8
SPISTAT - STATUS REGISTER
8
8032 MCU DATA BUS
CLOCK
GENERATE
SPISEL / P1.7 or P4.7
SPICLK / P1.4 or P4.4
CLOCK
DIVIDE
÷1
÷4
÷8
÷16
÷32
÷64
÷128
SPICLKD - DIVIDE SELECT
8
PERIPH_CLK
AI10486



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