UPSD3312D datasheet(147/272 Pages) STMICROELECTRONICS

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UPSD33xx

Synchronous peripheral interface (SPI)

Doc ID 9685 Rev 7

147/272

Table 85.

SPICON0: Control register 0 (SFR D6h, Reset Value 00h)

Table 86.

SPICON0 register bit definition

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

SPIEN

SSEL

FLSB

SBO

–

Bit

Symbol

R/W

Definition

–

Reserved

6TE

Transmitter Enable

0 = Transmitter is disabled

1 = Transmitter is enabled

5RE

Receiver Enable

0 = Receiver is disabled

1 = Receiver is enabled

SPIEN

SPI Enable

0 = Entire SPI Interface is disabled

1 = Entire SPI Interface is enabled

3SSEL

Slave Selection

0 = SPISEL output pin is constant logic '1' (slave device not

selected)

1 = SPISEL output pin is logic '0' (slave device is selected)

during data transfers

2FLSB

First LSB

0 = Transfer the most significant bit (MSB) first

1 = Transfer the least significant bit (LSB) first

SPO

–

Sampling Polarity

0 = Sample transfer data at the falling edge of clock (SPICLK

is '0' when idle)

1 = Sample transfer data at the rising edge of clock (SPICLK is

'1' when idle)

–

Reserved

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