UPSD3312D datasheet(146/272 Pages) STMICROELECTRONICS

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Synchronous peripheral interface (SPI)

UPSD33xx

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Doc ID 9685 Rev 7

24.5

SPI configuration

The SPI interface is reset by the MCU reset, and firmware needs to initialize the SFRs

SPICON0, SPICON1, and SPICLKD to define several operation parameters.

The SPO Bit in SPICON0 determines the clock polarity. When SPO is set to '0,' a data bit is

transmitted on SPITxD from one rising edge of SPICLK to the next and is guaranteed to be

valid during the falling edge of SPICLK. When SPO is set to '1,' a data bit is transmitted on

SPITxD from one falling edge of SPICLK to the next and is guaranteed to be valid during the

rising edge of SPICLK. The UPSD33xx will sample received data on the appropriate edge of

SPICLK as determined by SPO. The effect of the SPO Bit can be seen in Figure 42 on

page 144 and Figure 43 on page 144.

The FLSB Bit in SPICON0 determines the bit order while transmitting and receiving the 8-bit

data. When FLSB is '0,' the 8-bit data is transferred in order from MSB (first) to LSB (last).

When FLSB Bit is set to '1,' the data is transferred in order from LSB (first) to MSB (last).

The clock signal generated on SPICLK is derived from the internal PERIPH_CLK signal.

PERIPH_CLK always operates at the frequency, fOSC, and runs constantly except when

stopped in MCU Power-down mode. SPICLK is a result of dividing PERIPH_CLK by a sum

of different divisors selected by the value contained in the SPICLKD register. The default

value in SPICLKD after a reset divides PERIPH_CLK by a factor of 4. The bits in SPICLKD

can be set to provide resulting divisor values in of sums of multiples of 4, such as 4, 8, 12,

16, 20, all the way up to 252. For example, if SPICLKD contains 0x24, SPICLK has the

frequency of PERIH_CLK divided by 36 decimal.

The SPICLK frequency must be set low enough to allow the MCU time to read received data

bytes without loosing data. This is dependent upon many things, including the crystal

frequency of the MCU and the efficiency of the SPI firmware.

24.6

Dynamic control

At runtime, bits in registers SPICON0, SPICON1, and SPISTAT are managed by firmware

for dynamic control over the SPI interface. The bits Transmitter Enable (TE) and Receiver

Enable (RE) when set will allow transmitting and receiving respectively. If TE is disabled,

both transmitting and receiving are disabled because SPICLK is driven to constant output

logic ‘0’ (when SPO = 0) or logic '1' (when SPO = 1).

When the SSEL Bit is set, the SPISEL pin will drive to logic '0' (active) to select a connected

slave device at the appropriate time before the first data bit of a byte is transmitted, and

SPISEL will automatically return to logic '1' (inactive) after transmitting the eight bit of data,

as shown in Figure 43 on page 144. SPISEL will continue to automatically toggle this way

for each byte data transmission while the SSEL bit is set by firmware. When the SSEL Bit is

cleared, the SPISEL pin will drive to constant logic '1' and stay that way (after a transmission

in progress completes).

The Interrupt Enable Bits (TEIE, RORIE,TIE, and RIE) when set, will allow an SPI interrupt

to be generated to the MCU upon the occurrence of the condition enabled by these bits.

Firmware must read the four corresponding flags in the SPISTAT register to determine the

specific cause of interrupt. These flags are automatically cleared when firmware reads the

SPISTAT register.

UPSD3312D Datasheet(PDF) 146 Page - STMicroelectronics

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