UPSD3312D datasheet(142/272 Pages) STMICROELECTRONICS

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Synchronous peripheral interface (SPI)

UPSD33xx

142/272

Doc ID 9685 Rev 7

Figure 40.

SPI device connection examples

24.1

SPI bus features and communication flow

The SPICLK signal is a gated clock generated from the UPSD33xx (Master) and regulates

the flow of data bits. The Master may transmit at a variety of baud rates, and the SPICLK

signal will clock one period for each bit of transmitted data. Data is shifted on one edge of

SPICLK and sampled on the opposite edge.

The SPITxD signal is generated by the Master and received by the Slave device. The

SPIRxD signal is generated by the Slave device and received by the Master. There may be

no more than one Slave device transmitting data on SPIRxD at any given time in a multi-

Slave configuration. Slave selection is accomplished when a Slave’s “Slave Select” (SS)

input is permanently grounded or asserted active-low by a Master device. Slave devices that

are not selected do not interfere with SPI activities. Slave devices ignore SPICLK and keep

their MISO output pins in high-impedance state when not selected.

The SPI specification allows a selection of clock polarity and clock phase with respect to

data. The UPSD33xx supports the choice of clock polarity, but it does not support the choice

of clock phase (phase is fixed at what is typically known as CPHA = 1). See Figure 42 and

Figure 43 on page 144 for SPI data and clock relationships.

Referring to these figures (42 and 43), when the phase mode is defined as such (fixed at

CPHA =1), in a new SPI data frame, the Master device begins driving the first data bit on

SPITxD at the very first edge of the first clock period of SPICLK.

The Slave device will use this first clock edge as a transmission start indicator, and therefore

the Slave’s Slave Select input signal may remain grounded in a single-Master/single-Slave

SPI Bus

SPITxD

SPIRxD

UPSD33xx

SPI Master

SPI Slave

Device

SPICLK

SPISEL

AI07853c

MOSI

MISO

SCLK

Single-Master/Single-Slave, with SPISEL

Single-Master/Single-Slave, without SPISEL

Single-Master/Multiple-Slave, without SPISEL

SPI Slave

Device

MOSI

MISO

SCLK

SPI Slave

Device

MOSI

MISO

SCLK

SPITxD

SPIRxD

UPSD33xx

SPI Master

SPI Slave

Device

SPICLK

SPITxD

SPIRxD

UPSD33xx

SPI Mastecc

SPICLK

GPIO or PLD

MOSI

MISO

SCLK

UPSD3312D Datasheet(PDF) 142 Page - STMicroelectronics

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