UPSD3312D datasheet(167/272 Pages) STMICROELECTRONICS

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UPSD33xx

PSD module

Doc ID 9685 Rev 7

167/272

management, to READ/WRITE macrocells inside the General PLD, and other functions

during runtime. Unused locations within csiop are reserved and should not be accessed.

27.1.7

Memory page register

8032 MCU architecture has an inherent size limit of 64 Kbytes in either program address

space or XDATA space. Some UPSD33xx devices have much more memory that 64 Kbytes,

so special logic such as this page register is needed to access the extra memory. This 8-bit

page register (Figure 51) can be loaded and read by the 8032 at runtime as one of the csiop

registers. Page register outputs feed directly into both PLDs creating extended address

signals used to “page” memory beyond the 64 Kbyte limit (program space or XDATA). Most

8051 compilers directly support memory paging, also known as memory banking. If memory

paging is not needed, or if not all eight page register bits are needed for memory paging, the

remaining bits may be used in the General PLD for general logic. Page register outputs are

cleared to logic ’0’ at reset and power-up.

27.1.8

Programmable logic (PLDs)

The UPSD33xx contains two PLDs (Figure 62 on page 195) that may optionally run in Turbo

or Non-Turbo mode. PLDs operate faster (less propagation delay) while in Turbo mode but

consume more power than in Non-Turbo mode. Non-Turbo mode allows the PLDs to go to

standby automatically when no PLD inputs are changing to conserve power.

The logic configuration (from equations) of both PLDs is stored with non-volatile Flash

technology and the logic is active upon power-up. PLDs may NOT be programmed by the

8032, PLD programming only occurs through the JTAG interface.

Figure 51.

Memory Page register

27.1.9

PLD #1, Decode PLD (DPLD)

This programmable logic implements memory mapping and is used to select one of the

individual main Flash memory segments, one of individual secondary Flash memory

segments, the SRAM, or the group of csiop registers when the 8032 presents an address to

DPLD inputs (see Figure 63 on page 197). The DPLD can also optionally drive external chip

select signals on Port D pins. The DPLD also optionally produces two select signals (PSEL0

8032

Data

Bus

Load or

Read via

csiop +

offset E0h

DPLD

and

GPLD

Page

Chip-

Selects

and

General

Logic

RST

(PSD Module Reset)

RST

PGR0-7

AI09172

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