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UPSD3312D Datasheet(PDF) 171 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 171 Page - STMicroelectronics |
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171 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx PSD module Doc ID 9685 Rev 7 171/272 27.2 Memory mapping There many different ways to place (or map) the address range of PSD module memory and I/O depending on system requirements. The DPLD provides complete mapping flexibility. Figure 52 shows one possible system memory map. In this example, 128 Kbytes of main Flash memory for a UPSD3333 device is in 8032 program address space, and 32 Kbytes of secondary Flash memory, the SRAM, and csiop registers are all in 8032 XDATA space. In Figure 52, the nomenclature fs0..fs7 are designators for the individual sectors of main Flash memory, 16 Kbytes each. CSBOOT0..CSBOOT3 are designators for the individual secondary Flash memory segments, 8 Kbytes each. rs0 is the designator for SRAM, and csiop designates the PSD module control register set. The designer may easily specify memory mapping in a point-and-click software environment using PSDsoft Express, creating a non-volatile configuration when the DPLD is programmed using JTAG. 27.2.1 8032 program address space In the example of Figure 52, six sectors of main Flash memory (fs2.. fs7) are paged across three memory pages in the upper half of program address space, and the remaining two sectors of main Flash memory (fs0, fs1) reside in the lower half of program address space, and these two sectors are independent of paging (they reside in “common” program address space). This paged memory example is quite common and supported by many 8051 software compilers. 27.2.2 8032 data address space (XDATA) Four sectors of secondary Flash memory reside in the upper half of 8032 XDATA space in the example of Figure 52. SRAM and csiop registers are in the lower half of XDATA space. The 8032 SFR registers and local SRAM inside the 8032 MCU module do not reside in XDATA space, so it is OK to place PSD module SRAM or csiop registers at an address that overlaps the address of internal 8032 MCU module SRAM and registers. Figure 52. Typical system memory map 0000h 8000h A000h C000h E000h FFFFh 8032 XDATA SPACE (RD and WR) 8032 PROGRAM SPACE (PSEN) csboot0 8KB csboot1 8KB csboot2 8KB csboot3 8KB Page X fs0, 16KB Common Memory to All Pages fs7 16KB fs5 16KB fs3 16KB rs0, 8KB Page 0 Page 2 Page 1 2000h 0000h 8000h FFFFh System I/O fs6 16KB fs4 16KB fs2 16KB fs1, 16KB Common Memory to All Pages C000h 4000h csiop 256B AI09173 |
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