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UPSD3312D Datasheet(PDF) 243 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 243 Page - STMicroelectronics |
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243 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx AC/DC parameters Doc ID 9685 Rev 7 243/272 Figure 85. PLD ICC /frequency consumption (3 V range) 0 10 20 30 40 50 60 VCC = 3V 010 15 5 20 25 TURBO ON (100%) TURBO ON (25%) TURBO OFF HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) PT 100% PT 25% AI03100 Table 159. PSD module example, typ. power calculation at VCC = 5.0 V (Turbo mode Off) Conditions MCU Clock Frequency = 12 MHz Highest Composite PLD input frequency (Freq PLD) = 8 MHz MCU ALE frequency (Freq ALE) = 2 MHz % Flash memory Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational modes % Normal = 40% % Power-down mode = 60% Number of product terms used (from fitter report) = 45 PT % of total product terms = 45/182 = 24.7% Turbo mode = Off Calculation (using typical values) ICC total = ICC(MCUactive) x %MCUactive + ICC(PSDactive) x %PSDactive + IPD(pwrdown) x %pwrdown |
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