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UPSD3312D Datasheet(PDF) 242 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 242 Page - STMicroelectronics |
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242 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) AC/DC parameters UPSD33xx 242/272 Doc ID 9685 Rev 7 28 AC/DC parameters These tables describe the AD and DC parameters of the UPSD33xx Devices: ● DC electrical specification ● AC timing specification ● PLD timing – Combinatorial timing – Synchronous Clock mode – Asynchronous Clock mode – Input macrocell timing ● MCU module timing – READ timing –WRITE timing – Power-down and RESET timing The following are issues concerning the parameters presented: ● In the DC specification the supply current is given for different modes of operation. ● The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 84 and Figure 85 on page 243 show the PLD mA/MHz as a function of the number of Product Terms (PT) used. ● In the PLD timing parameters, add the required delay when Turbo Bit is '0.' Figure 84. PLD ICC /frequency consumption (5 V range) 0 10 20 30 40 60 70 80 90 100 110 VCC = 5V 50 010 15 5 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) TURBO ON (100%) TURBO ON (25%) TURBO OFF PT 100% PT 25% AI02894 |
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