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UPSD3312D Datasheet(PDF) 238 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 238 Page - STMicroelectronics |
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238 / 272 page  Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) PSD module UPSD33xx 238/272 Doc ID 9685 Rev 7 Figure 81. Recommended 6-pin JTAG connections 1. For 5 V UPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 5 V system VDD. 2. For 3.3 V UPSD33xx devices, pull-up resistors and VCC pin on the JTAG connector should be connected to 3.3 V system VCC. 3. This signal is driven by an Open-Drain output in the JTAG equipment, allowing more than one source to activate RESET_IN. TMS - PC0 TCK - PC1 I/O - PC2 GENERAL I/O - PC3 GENERAL I/O - PC4 TDI - PC5 TDO - PC6 GENERAL I/O - PC7 JTAG CONN. 100k typical TMS TCK TDI TDO GENERAL I/O SIGNALS GND VCC (1,2) RST (3) UPSD33XX 0.01 µF CIRCUIT BOARD JTAG Programming or Test Equipment Connects Here 10k PUSH BUTTON or ANY OTHER RESET SOURCE DEBUG OPTIONAL TEST POINT 100k RESETIN AI09185c |
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