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UPSD3312D Datasheet(PDF) 235 Page - STMicroelectronics |
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UPSD3312D Datasheet(HTML) 235 Page - STMicroelectronics |
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235 / 272 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) UPSD33xx PSD module Doc ID 9685 Rev 7 235/272 Figure 79. JTAG chain in UPSD33xx package 27.5.3 In-system programming The ISP function can use two different configurations of the JTAG interface: ● 4-pin JTAG: TDI, TDO, TCK, TMS ● 6-pin JTAG: Signals above plus TSTAT, TERR At power-up, the four basic JTAG signals are all inputs, waiting for a command to appear on the JTAG bus from programming or test equipment. When the enabling command is received, TDO becomes an output and the JTAG channel is fully functional. The same command that enables the JTAG channel may optionally enable the two additional signals, TSTAT and TERR. JTAG TDI JTAG TMS JTAG TCK JTAG TDO TDI TMS TCK TDO TDO TMS TCK TDI PC3 / TSTAT PC4 / TERR TSTAT TERR OPTIONAL JTAG TAP CONTROLLER JTAG TAP CONTROLLER RESET_IN OPTIONAL DEBUG RESET RST 8032 MCU MCU MODULE PSD MODULE MAIN FLASH MEMORY 2ND FLASH MEMORY PLD UPSD33XX IEEE 1149.1 AI09184b |
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