UPSD3312D datasheet(232/272 Pages) STMICROELECTRONICS

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PSD module

UPSD33xx

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Doc ID 9685 Rev 7

The user can also block an input signal coming from pin PC7 to the PLD input bus if desired

by writing to Bit 6 of PMMR2.

27.4.61

Blocking common clock, CLKIN

The input CLKIN (from pin PD1) can be blocked to reduce current consumption. CLKIN is

used as a common clock input to all OMC flip-flips, it is a general input to the PLD input bus,

and it is used to clock the APD counter. In PSDsoft Express, the function of pin PD1 must be

specified as “Common Clock Input, CLKIN” before programming the device with JTAG to get

the CLKIN function.

Bit 4 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the PLD input bus, but

CLKIN will still reach the APD counter.

Bit 5 of PMMR0 can be set to logic ’1’ to block CLKIN from reaching the OMC flip-flops only,

but CLKIN is still available to the PLD input bus and the APD counter.

See Table 154 on page 225 for details.

27.5

PSD module reset conditions

The PSD module receives a reset signal from the MCU module. This reset signal is referred

to as the “RST” input in PSD module documentation, and it is active-low when asserted. The

character of the RST signal generated from the MCU module is described in Section 19:

Supervisory functions on page 89.

Upon power-up, and while RST is asserted, the PSD module immediately loads its

configuration from non-volatile bits to configure the PLDs and other items. PLD logic is

operational and ready for use well before RST is de-asserted. The state of PLD outputs are

determined by equations specified in PSDsoft Express.

The Flash memories are reset to Read Array mode after any assertion of RST (even if a

program or erase operation is occurring).

Flash memory WRITE operations are automatically prevented while VDD is ramping up until

it rises above the VLKO voltage threshold at which time Flash memory WRITE operations

are allowed.

Once the UPSD33xx is up and running, any subsequent reset operation is referred to as a

warm reset, until power is turned off again. Some PSD module functions are reset in

different ways depending if the reset condition was caused from a power-up reset or a warm

reset. Table 158 on page 233 summarizes how PSD module functions are affected by

power-up and warm resets, as well as the affect of PSD module power-down mode (from

APD).

The I/O pins of PSD module Ports A, B, C, and D do not have weak internal pull-ups.

In MCU I/O mode, Latched Address Out mode, and Peripheral I/O mode, the pins of Ports

A, B, C, and D become standard CMOS inputs during a reset condition. If no external

devices are driving these pins during reset, then these inputs may float and draw excessive

current. If low power consumption is critical during reset, then these floating inputs should

be pulled up externally to VDD with a weak (100KΩ minimum) resistor.

In PLD I/O mode, pins of Ports A, B, C, and D may also float during reset if no external

device is driving them, and if there is no equation specified for the DPLD or GPLD to make

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