UPSD3312D datasheet(230/272 Pages) STMICROELECTRONICS

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Doc ID 9685 Rev 7

27.4.54

Chip Select Input (CSI)

Pin PD2 of Port D can optionally be configured in PSDsoft Express as the PSD module Chip

Select Input, CSI, which is an active-low logic input. By default, pin PD2 does not have the

CSI function.

When the CSI function is specified in PSDsoft Express, the CSI signal is automatically

included in DPLD chip select equations for FSx, CSBOOTx, RS0, and CSIOP. When the CSI

pin is driven to logic ’0’ from an external device, all of these memories will be available for

READ and WRITE operations. When CSI is driven to logic '1,' none of these memories are

available for selection, regardless of the address activity from the 8032, reducing power

consumption. The state of the PLD and port I/O pins are not changed when CSI goes to

logic ’1’ (disabled).

27.4.55

PLD non-turbo mode

The power consumption and speed of the PLDs are controlled by the Turbo Bit (Bit 3) in the

csiop PMMR0 register. By setting this bit to logic '1,' the Turbo mode is turned off and both

PLDs consume only standby current when ALL PLD inputs have no transitions for an

extended time (65ns for 5 V devices, 100ns for 3.3 V devices), significantly reducing current

consumption. The PLDs will latch their outputs and go to standby, drawing very little current.

When Turbo mode is off, PLD propagation delay time is increased as shown in the AC

specifications for the PSD module. Since this additional propagation delay also effects the

DPLD, the response time of the memories on the PSD module is also lengthened by that

same amount of time. If Turbo mode is off, the user should add an additional wait state to the

8032 BUSCON SFR register if the 8032 clock frequency is higher that a particular value.

Please refer to Table 49 on page 88 in the MCU module section.

The default state of the Turbo Bit is logic '0,' meaning Turbo mode is on by default (after

power-up and reset conditions) until it is turned off by the 8032 writing to PMMR0.

27.4.56

PLD current consumption

Figure 84 and Figure 85 on page 243 (5 V and 3.3 V devices respectively) show the

relationship between PLD current consumption and the composite frequency of all the

transitions on PLD inputs, indicating that a higher input frequency results in higher current

consumption.

Current consumption of the PLDs have a DC component and an AC component. Both need

to be considered when calculating current consumption for a specific PLD design. When

Turbo mode is on, there is a linear relationship between current and frequency, and there is

a substantial DC current component consumed by the PSD module when there are no

transitions on PLD inputs (composite frequency is zero). The magnitude of this DC current

component is directly proportional to how many product terms are used in the equations of

both PLDs. PSDsoft Express generates a “fitter” report that specifies how many product

terms were used in a design out of a total of 186 available product terms. Figure 84 and

Figure 85 on page 243 both give two examples, one with 100% of the 186 product terms

used, and another with 25% of the 186 product terms used.

27.4.57

Turbo mode current consumption

To determine the AC current component of the specific PLD design with Turbo mode on, the

user will have to interpolate from the graph, given the number of product terms specified in

the fitter report, and the estimated composite frequency of PLD input signal transitions. For

UPSD3312D Datasheet(PDF) 230 Page - STMicroelectronics

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