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UPSD3312D Datasheet(PDF) 228 Page - STMicroelectronics

Part # UPSD3312D
Description  fast 8032 MCU with programmable logic
PDF  272 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

UPSD3312D Datasheet(HTML) 228 Page - STMicroelectronics

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Doc ID 9685 Rev 7
27.4.53
Forced Power-down (FDP)
An alternative to APD is FPD. The resulting power-savings is the same, but the PDN signal
in Figure 77 on page 229 is set and Power-down mode is entered immediately when
firmware sets the FORCE_PD Bit to logic '1' in the csiop register PMMR3 (Bit 1). FPD will
override APD counter activity when FORCE_PD is set. No external clock source for the APD
counter is needed. The FORCE_PD Bit is cleared only by a reset condition.
Caution must be used when implementing FPD because code memory goes off-line as
soon as PSD module Power-down mode is entered, leaving the MCU with no instruction
stream to execute.
The MCU module must put itself into Power-down mode after it puts the PSD module into
Power-down mode. How can it do this if code memory goes off-line? The answer is the Pre-
Fetch Queue (PFQ) in the MCU module. By using the instruction scheme shown in the 8051
assembly code example in Table 157 on page 228, the PFQ will be loaded with the final
instructions to command the MCU module to Power-down mode after the PDS module goes
to Power-down mode. In this case, even though the code memory goes off-line in the PSD
module, the last few MCU instruction are sourced from the PFQ.
Table 157.
Forced Power-down example
PDOWN:
ANL
A8h, #7Fh
; disable all interrupts
ORL
9Dh, #C0h
; ensure PFQ and BC are enabled
MOV
DPTR, #xxC7
; load XDATA pointer to select PMMR3 register (xx
= base
; address of csiop registers)
CLR
A
; clear A
JMP
LOOP
; first loop - fill PFQ/BQ with Power-down
instructions
NOP
; second loop - fetch code from PFQ/BC and set
Power-
; Down bits for PSD module and then MCU
module
LOOP:
MOVX
@DPTR, A
; set FORCE_PD Bit in PMMR3 in PSD module in
second
; loop
MOV
87h, A
; set PD Bit in PCON register in MCU module in
second
; loop
MOV
A, #02h
; set power-down bit in the A register, but not in
PMMR3 or
; PCON yet in first loop
JMP
LOOP
; UPSD enters into Power-down mode in second
loop



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