UPSD3312D datasheet(225/272 Pages) STMICROELECTRONICS

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UPSD33xx

PSD module

Doc ID 9685 Rev 7

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no PLD inputs are changing, and the PLDs will even use less AC current when inputs do

change compared to Turbo mode.

When the Turbo mode is enabled, there is a significant DC current component AND the

AC current component is higher than non-Turbo mode, as shown in Figure 84 on

page 242 (5 V) and Figure 85 on page 243 (3.3 V).

Blocking bits

Significant power savings can be achieved by blocking 8032 bus control signals (RD, WR,

PSEN, ALE) from reaching PLD inputs, if these signals are not used in any PLD equations.

Blocking is achieved by the 8032 writing to the “blocking bits” in csiop PMMR registers.

Current consumption of the PLDs is directly related to the composite frequency of all

transitions on PLD inputs, so blocking certain PLD inputs can significantly lower PLD

operating frequency and power consumption (resulting in a lower frequency on the graphs of

Figure 84 on page 242 and Figure 85 on page 243).

Note:

It is recommended to prevent unused inputs from floating on Ports A, B, C, and D by pulling

them up to VDD with a weak external resistor (100 KΩ), or by setting the csiop Direction

of unused input pins from drawing excessive current.

The csiop PMMR register definitions are shown in Table 154 through Table 156 on

page 226.

Table 154.

Power Management Mode register PMMR0 (address = csiop + offset B0h)(1)

Bit

num.

Bit name

Value

Description

Bit 0

Not used, and should be set to zero.

Bit 1

APD Enable

Automatic Power-down (APD) counter is disabled.

APD counter is enabled

Bit 2

Not used, and should be set to zero.

Bit 3

PLD Turbo

Disable

0 = on PLD Turbo mode is on

1 = off PLD Turbo mode is off, saving power.

Bit 4

Blocking bit,

CLKIN to

PLDs(2)

0 = on

CLKIN (pin PD1) to the PLD Input Bus is not blocked. Every transition of CLKIN

powers-up the PLDs.

1 = off

CLKIN input to PLD Input Bus is blocked, saving power. But CLKIN still goes to

APD counter.

Bit 5

Blocking bit,

CLKIN to

OMCs only(2)

0 = on CLKIN input is not blocked from reaching all OMC’s common clock inputs.

1 = off

CLKIN input to common clock of all OMCs is blocked, saving power. But CLKIN

still goes to APD counter and all PLD logic besides the common clock input on

OMCs.

Bit 6

Not used, and should be set to zero.

Bit 7

Not used, and should be set to zero.

All the bits of this register are cleared to zero following Power-up. Subsequent Reset (RST) pulses do not clear the

registers.

Blocking bits should be set to logic ’1’ only if the signal is not needed in a DPLD or GPLD logic equation.

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