UPSD3312D datasheet(222/272 Pages) STMICROELECTRONICS

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UPSD33xx

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Doc ID 9685 Rev 7

Figure 75.

Port C structure

Optional function on a specific Port C pin.

27.4.50

Port D structure

Port D has two I/O pins (PD1, PD2) on 80-pin UPSD33xx devices, and just one pin (PD1) on

52-pin devices, supporting the following operating modes:

●

MCU I/O mode

●

DPLD Output mode for External Chip Selects, ECS1, ECS2. This does not consume

OMCs in the GPLD.

●

PLD Input mode – direct input to the PLD Input Bus available to DPLD and GPLD. Does

not use IMCs

See Figure 76 on page 223 for detail.

I/O PORT C

LOGIC

DIRECTION

DRIVE SELECT

DATA OUT

(MCUI/O)

ENABLE OUT

DATA IN (MCUI/O)

PT OUTPUT ENABLE, .OE (JTAG STATE MACHINE

AUTOMATICALLY CONTROLS OE FOR JTAG SIGNALS)

OUTPUT

ENABLE

TYPICAL

PIN,

PORT C

PSD MODULE RESET

ONE of 6

CSIOP

REGISTERS

FROM OMC OUTPUT (MCELLBCx)

STANDBY ON

(1)

FROM SRAM

BACK-UP CIRCUIT

FROM FLASH MEMORIES

TO/FROM JTAG

STATE MACHINE

FROM PLD

INPUT BUS

FROM AND-

OR ARRAY

FROM OMC

ALLOCATOR

CLR

DIRECTION

DRIVE

(MCUI/O)

DATA OUT

8032

RESET

PSDsoft

8032 RD

TO IMCs

CSIOP

REGIS-

TERS

DRIVE TYPE SELECT

(1)

8032

DATA

BITS

8032

DATA

BIT

INPUT

CMOS

BUFFER

HYSTERESIS

VDD

OUTPUT

50k

PULL-UP

ONLY ON

JTAG TDI,

TMS, TCK

SIGNALS

IMCC2, IMCC3,

IMCC4, IMCC7

RDY/BSY

(1)

TDO, TSTAT

(1), TERR(1)

TDI, TMS, TCK

AI09181b

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