UPSD3312D datasheet(219/272 Pages) STMICROELECTRONICS

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UPSD33xx

PSD module

Doc ID 9685 Rev 7

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Figure 73.

Port A structure

Port pins PA0-PA3 are capable of Fast Slew Rate output drive option. Port pins PA4-PA7 are capable of Open Drain output

option.

27.4.48

Port B structure

Port B supports the following operating modes:

●

MCU I/O mode

●

GPLD Output mode from Output Macrocells MCELLABx, or MCELLBCx (OMC

allocator routes these signals)

●

GPLD Input mode to Input Macrocells IMCBx

●

Latched Address Output mode

Port B also supports Open Drain/Slew Rate output drive type options using the csiop Drive

Select registers. Pins PB0-PB3 can be configured to fast slew rate, pins PB4-PB7 can be

configured to Open Drain mode.

See Figure 74 on page 220 for details.

I/O PORT A

LOGIC

DIRECTION

DRIVE SELECT

CONTROL

DATA OUT

(MCUI/O)

ENABLE OUT

DATA IN (MCUI/O)

D BIT, PERIPH I/O MODE

PT OUTPUT ENABLE (.OE)

LATCHED ADDR BIT

MUX

OUTPUT

ENABLE

TYPICAL

PIN, PORT A

PSD MODULE RESET

ONE of 6

CSIOP

REGISTERS

OUTPUT

SELECT

PERIPHERAL I/O

MODE SETS

DIRECTION

FROM OMC OUTPUT (MCELLABx)

FROM PLD

INPUT BUS

FROM AND-

OR ARRAY

FROM OMC

ALLOCATOR

CLR

DIRECTION

DRIVE

CONTROL

(MCUI/O)

DATA OUT

8032

RESET

PSDsoft

8032 RD

PSELx

PERIPH I/O

DATA BIT

TO IMCs

PIO EN

CSIOP

REGIS-

TERS

DRIVE TYPE SELECT

(1)

8032

DATA

BITS

8032

DATA

BIT

PIN INPUT

CMOS

BUFFER

HYSTERESIS

VDD

OUTPUT

1 = OPEN

DRAIN,

PA4 - PA7

1 = FAST

SLEW RATE,

PA0 - PA3

IMCA0 - IMCA7

AI09179

UPSD3312D Datasheet(PDF) 219 Page - STMicroelectronics

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