UPSD3312D datasheet(224/272 Pages) STMICROELECTRONICS

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PSD module

UPSD33xx

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Doc ID 9685 Rev 7

27.4.51

Power management

The PSD module offers configurable power saving options. These options may be used

individually or in combinations. A top level description for these functions is given here, then

more detailed descriptions will follow.

Zero-Power memory

All memory arrays (Flash and SRAM) in the PSD module are built with zero-power

technology, which puts the memories into standby mode (~ zero DC current) when 8032

address signals are not changing. As soon as a transition occurs on any address input, the

affected memory “wakes up”, changes and latches its outputs, then goes back to standby.

The designer does not have to do anything special to achieve this memory standby mode

when no inputs are changing—it happens automatically. Thus, the slower the 8032 clock,

the lower the current consumption.

Both PLDs (DPLD and GPLD) are also zero-power, but this is not the default condition. The

8032 must set a bit in one of the csiop PMMR registers at run-time to achieve zero-power.

Automatic Power-down (APD)

The APD feature allows the PSD module to reach it’s lowest current consumption levels. If

enabled, the APD counter will timeout when there is a lack of 8032 bus activity for an

extended amount of time (8032 asleep). After timeout occurs, all 8032 address and data

buffers on the PSD module are shut down, preventing the PSD module memories and

potentially the PLDs from waking up from standby, even if address inputs are changing state

because of noise or any external components driving the address lines. Since the actual

address and data buffers are turned off, current consumption is even further reduced.

The APD counter requires a relatively slow external clock input on pin PD1 that does stop

when the 8032 goes to sleep mode.

Note:

Non-address signals are still available to PLD inputs and will wake up the PLDs if these

signals are changing state, but will not wake up the memories.

Forced Power-down (FPD)

The MCU can put the PSD module into Power-down mode with the same results as using

APD described above, but FPD does not rely on the APD counter. Instead, FPD will force

the PSD module into Power-down mode when the MCU firmware sets a bit in one of the

csiop PMMR registers. This is a good alternative to APD because no external clock is

needed for the APD counter.

PSD module Chip Select Input (CSI)

This input on pin PD2 (80-pin devices only) can be used to disable the internal memories,

placing them in standby mode even if address inputs are changing. This feature does not

block any internal signals (the address and data buffers are still on but signals are ignored)

and CSI does not disable the PLDs. This is a good alternative to using the APD counter,

which requires an external clock on pin PD1.

Non-Turbo mode

The PLDs can operate in Turbo or non-Turbo modes. Turbo mode has the shortest signal

propagation delay, but consumes more current than non-Turbo mode. A csiop register can

be written by the 8032 to select modes, the default mode is with Turbo mode enabled. In

non-Turbo mode, the PLDs can achieve very low standby current (~ zero DC current) while

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