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CP3SP33SMS/NOPB Datasheet(PDF) 326 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 326 Page - Texas Instruments

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Timer/Counter 1
TCNT1_n
Timer 1
Clock
Reload A
TCRA_n
TAPND
TAIEN
Timer
Interrupt 1
TAEN
TAn
TBn
Underflow
Timer/Counter 2
TCNT2_n
Timer 2
Clock
Reload B
TCRB_n
TDPND
TDIEN
Timer
Interrupt 2
Underflow
Clock
Selector
DS453
CP3SP33
SNOSCW5 – MAY 2013
www.ti.com
32.2.3 Mode 3: Dual Independent Timer/Counter
Mode 3 is the Dual Independent Timer mode, which generates system timing signals or counts
occurrences of exter- nal events.
Figure 32-6 is a block diagram of the Multi-Function Timer configured to operate in Mode 3. The timer is
configured to operate as a dual independent system timer or dual external event counter. In addition,
Timer/Counter 1 can generate a 50% duty cycle PWM signal on the TAn pin. The TBn pin can be used as
an external event input or pulse-accumulate input and can be used as the clock source for either Timer/
Counter 1 or Timer/Counter 2. Both counters can also be clocked by the prescaled PCLK Clock.
Timer/Counter 1 (TCNT1_n) counts down at the rate of the selected clock. On underflow, it is reloaded
from the TCRA_n register and counting proceeds down from the reloaded value. In addition, the TAn pin
is toggled on each underflow if this function is enabled by the TAEN bit. The initial state of the TAn pin is
software-programmable. When the TAn pin is toggled from low to high, it sets the TCPND interrupt
pending bit and also asserts an interrupt if enabled by the TAIEN bit.
Because the TAn pin toggles on every underflow, a 50% duty cycle PWM signal can be generated on the
TAn pin without any further action from the CPU.
Timer/Counter 2 (TCNT2_n) counts down at the rate of the selected clock. On underflow, it is reloaded
from the TCRB_n register and counting proceeds down from the reloaded value. In addition, each
underflow sets the TDPND interrupt pending bit and asserts an interrupt if the interrupt is enabled by the
TDIEN bit.
Figure 32-6. Dual-Independent Timer/Counter Mode
326
Dual Multi-Function Timers
Copyright © 2013, Texas Instruments Incorporated
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