CP3SP33SMSSLASHNOPB datasheet(323/407 Pages) TI1

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Prescaler

Output

TBn

Counter

Clock

DS450

CP3SP33

www.ti.com

SNOSCW5 – MAY 2013

32.1.2.4 Pulse Accumulate Mode

The counter can also be configured to count prescaler output clock pulses when the TBn input is high and

not count when the TBn input is low, as illustrated in Figure 32-3. The resulting count is an indicator of the

cumulative time that the TBn input is high. This is called the "pulse-accumulate" mode. In this mode, an

AND gate generates a clock signal for the counter whenever a prescaler clock pulse is generated and the

TBn input is high. (The polarity of the TBn signal is programmable, so the counter can count when the

TBn input is low rather than high.) The pulse-accumulate mode is not available in the capture modes

(modes 2 and 4) because the TBn pin is used as one of the two capture inputs.

Figure 32-3. Pulse-Accumulate Mode

32.1.2.5 Slow Clock

Slow Clock can be selected as the clock source for the two 16-bit counters. Because Slow Clock can be

asynchronous, it must be synchronized to PCLK Clock, therefore the maximum input frequency of Slow

Clock is the PCLK Clock fre- quency divided by four.

32.1.2.6 Limitations in Low-Power Modes

The Power Save mode drives Slow Clock onto HCLK Clock. In this mode, Slow Clock cannot be used as

a clock source for the timers because it would have the same frequency or a higher frequency than PCLK

Clock, and the clock ratio needed for synchronization to PCLK Clock would not be maintained. However,

the External Event Clock and Pulse Accumulate Mode will still work, as long as the external event pulses

are at least the length of the PCLK Clock period.

Idle and Halt modes stop HCLK Clock and PCLK Clock. If PCLK Clock is stopped, the timer stops

counting until PCLK Clock resumes operation.

32.2 Timer Operating Modes

Each timer/counter unit can be configured to operate in the following modes:

•

Processor-Independent Pulse Width Modulation (PWM) mode

•

Dual-Input Capture mode

•

Dual Independent Timer mode

•

Single-Input Capture and Single Timer mode

At reset, the timers are disabled. To configure and start the timers, software must write a set of values to

the registers that control the timers. The registers are described in Section Section 32.4

32.2.1 Mode 1: Processor-Independent PWM

Mode 1 is the Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a

specified width and duty cycle, and which also provides a separate general-purpose timer/counter.

Dual Multi-Function Timers

323

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