CP3SP33SMSSLASHNOPB datasheet(327/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

32.2.4 Mode 4: Input Capture Plus Timer

Mode 4 is the Single Input Capture and Single Timer mode, which provides one external event counter

and one system timer.

Figure 32-7 is a block diagram of the Multi-Function Timer configured to operate in Mode 4. This mode

offers a combination of Mode 3 and Mode 2 functions. Timer/Counter 1 is used as a system timer as in

Mode 3 and Timer/Counter 2 is used as a capture timer as in Mode 2, but with a single input rather than

two inputs.

Timer/Counter 1 (TCNT1_n) operates the same as in Mode 3. It counts down at the rate of the selected

clock. On underflow, it is reloaded from the TCRA_n register and counting proceeds down from the

reloaded value. The TAn pin is toggled on each underflow, when this function is enabled by the TAEN bit.

When the TAn pin is toggled from low to high, it sets the TCPND interrupt pending bit and also asserts an

interrupt if the interrupt is enabled by the TAIEN bit. A 50% duty cycle PWM signal can be generated on

TAn without any further action from the CPU.

Timer/Counter 2 (TCNT1_n) counts down at the rate of the selected clock. The TBn pin functions as the

capture input. A transition received on TBn transfers the timer contents to the TCRB_n register. The input

pin can be configured to sense either rising or falling edges.

The TBn input can be configured to preset the counter to FFFFh on reception of a valid capture event. In

this case, the current value of the counter is transferred to the capture register and then the counter is

preset to FFFFh.

The values captured in the TCRB_n register at different times reflect the elapsed time between transitions

on the TBn pin. The input signal on TBn must have a pulse width equal to or greater than one PCLK Clock

cycle.

There are two separate interrupts associated with the capture timer, each with its own enable bit and

pending bit. The two interrupt events are reception of a transition on TBn and underflow of the TCNT2_n

counter. The enable bits for these events are TBIEN and TDIEN, respectively.

Neither Timer/Counter 1 (TCNT1_n) nor Timer/Counter 2 (TCNT2_n) can be configured to operate as an

external event counter or to operate in the pulse-accumulate mode because the TBn input is used as a

capture input. Attempting to select one of these configurations will cause one or both counters to stop. In

this mode, Timer/Counter 2 must be enabled at all times.

Dual Multi-Function Timers

327

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CP3SP33SMS/NOPB Datasheet(PDF) 327 Page - Texas Instruments