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HT66F4530 Datasheet(PDF) 65 Page - Holtek Semiconductor Inc |
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HT66F4530 Datasheet(HTML) 65 Page - Holtek Semiconductor Inc |
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65 / 224 page  Rev. 1.00 �4 De�e��e� �1� �01� Rev. 1.00 �5 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers Bit1 LRF:LVRcontrolregistersoftwareresetflag Describedelsewhere. Bit0 WRF:WDTcontrolregistersoftwareresetflag 0:Notoccurred 1:Occurred Thisbitissetto1bytheWDTControlregistersoftwareresetandclearedbythe applicationprogram.Notethatthisbitcanonlybeclearedto0bytheapplication program. Watchdog Timer Operation TheWatchdogTimeroperatesbyprovidingadeviceresetwhenitstimeroverflows.Thismeans thatintheapplicationprogramandduringnormaloperationtheuserhastostrategicallyclearthe WatchdogTimerbeforeitoverflowstopreventtheWatchdogTimerfromexecutingareset.Thisis doneusingtheclearwatchdoginstructions.Iftheprogrammalfunctionsforwhateverreason,jumps toanunknownlocation,orentersanendlessloop,theseclearinstructionswillnotbeexecutedinthe correctmanner,inwhichcasetheWatchdogTimerwilloverflowandresetthesedevices.Thereare fivebits,WE4~WE0,intheWDTCregistertooffertheenable/disablecontrolandresetcontrolof theWatchdogTimer.TheWDTfunctionwillbedisabledwhentheWE4~WE0bitsaresettoavalue of10101BwhiletheWDTfunctionwillbeenablediftheWE4~WE0bitsareequalto01010B.If theWE4~WE0bitsaresettoanyothervalues,otherthan01010Band10101B,itwillresetthese devicesaftertSRESETtime.Afterpoweronthesebitswillhaveavalueof01010B. WE4~WE0 Bits WDT Function 10101B Disa�le 01010B Ena�le Any othe� values Reset MCU Watchdog Timer Enable/Disable Control Undernormalprogramoperation,aWatchdogTimertime-outwillinitialiseadeviceresetandsetthe statusbitTO.However,ifthesystemisintheSLEEPorIDLEMode,whenaWatchdogTimertime- outoccurs,theTObitinthestatusregisterwillbesetandonlytheProgramCounterandStackPointer willbereset.FourmethodscanbeadoptedtoclearthecontentsoftheWatchdogTimer.Thefirstisa WDTreset,whichmeansacertainvalueexcept01010Band10101BwrittenintotheWE4~WE0bits, thesecondisusingtheWatchdogTimersoftwareclearinstruction,thethirdisviaaHALTinstruction andthefourthisanexternalhardwarereset,whichmeansalowlevelontheexternalRESpin. ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse thesingle"CLRWDT"instructiontocleartheWDT. Themaximumtimeoutperiodiswhenthe218divisionratioisselected.Asanexample,witha 32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8 secondforthe218divisionratio,andaminimumtimeoutof7.8msforthe28divisionration. “CLR WDT” Inst�u�tion WE4~WE0 �its WDTC Registe� Reset MCU fLIRC CLR “HALT” Inst�u�tion 8-stage Divide� WDT P�es�ale� fLIRC/�8 8-to-1 MUX WS�~WS0 WDT Ti�e-out (�8/fLIRC ~ �18/fLIRC) RES pin �eset Watchdog Timer |
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