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HT66F4530 Datasheet(PDF) 95 Page - Holtek Semiconductor Inc |
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HT66F4530 Datasheet(HTML) 95 Page - Holtek Semiconductor Inc |
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95 / 224 page  Rev. 1.00 94 De�e��e� �1� �01� Rev. 1.00 95 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers IntheCompareMatchOutputMode,theSTnIO1andSTnIO0bitsdeterminehowthe STMnoutputpinchangesstatewhenacomparematchoccursfromtheComparator A.TheTMoutputpincanbesetuptoswitchhigh,switchlowortotoggleitspresent statewhenacomparematchoccursfromtheComparatorA.Whenthebitsareboth zero,thennochangewilltakeplaceontheoutput.TheinitialvalueoftheSTMn outputpinshouldbesetupusingtheSTnOCbitintheSTMnC1register.Notethat theoutputlevelrequestedbytheSTnIO1andSTnIO0bitsmustbedifferentfromthe initialvaluesetupusingtheSTnOCbitotherwisenochangewilloccurontheSTMn outputpinwhenacomparematchoccurs.AftertheSTMnoutputpinchangesstate, itcanberesettoitsinitiallevelbychangingtheleveloftheSTnONbitfromlowto high. InthePWMOutputMode,theSTnIO1andSTnIO0bitsdeterminehowtheSTMn outputpinchangesstatewhenacertaincomparematchconditionoccurs.ThePWM outputfunctionismodifiedbychangingthesetwobits.Itisnecessarytoonlychange thevaluesoftheSTnIO1andSTnIO0bitsonlyaftertheSTMnhasbeenswitchedoff. UnpredictablePWMoutputswilloccuriftheSTnIO1andSTnIO0bitsarechanged whentheSTMnisrunning. Bit3 STnOC:STMnSTPnOutputcontrol CompareMatchOutputMode 0:Initiallow 1:Initialhigh PWMOutputMode/SinglePulseOutputMode 0:Activelow 1:Activehigh ThisistheoutputcontrolbitfortheSTMnoutputpin.Itsoperationdependsupon whetherSTMnisbeingusedintheCompareMatchOutputModeorinthePWM OutputMode/SinglePulseOutputMode.IthasnoeffectiftheSTMnisintheTimer/ CounterMode.IntheCompareMatchOutputModeitdeterminesthelogiclevelof theSTMnoutputpinbeforeacomparematchoccurs.InthePWMOutputModeit determinesifthePWMsignalisactivehighoractivelow.IntheSinglePulseOutput ModeitdeterminesthelogicleveloftheSTMnoutputpinwhentheSTnONbit changesfromlowtohigh. Bit2 STnPOL:STMnSTPnOutputpolaritycontrol 0:Non-inverted 1:Inverted ThisbitcontrolsthepolarityoftheSTPnoutputpin.Whenthebitissethighthe STMnoutputpinwillbeinvertedandnotinvertedwhenthebitiszero.Ithasnoeffect iftheSTMnisintheTimer/CounterMode. Bit1 STnDPX:STMnPWMduty/periodcontrol 0:CCRP–period;CCRA–duty 1:CCRP–duty;CCRA–period ThisbitdetermineswhichoftheCCRAandCCRPregistersareusedforperiodand dutycontrolofthePWMwaveform. Bit0 STnCCLR:STMnCounterClearconditionselection 0:ComparatorPmatch 1:ComparatorAmatch Thisbitisusedtoselectthemethodwhichclearsthecounter.Rememberthatthe StandardTMcontainstwocomparators,ComparatorAandComparatorP,eitherof whichcanbeselectedtocleartheinternalcounter.WiththeSTnCCLRbitsethigh, thecounterwillbeclearedwhenacomparematchoccursfromtheComparatorA. Whenthebitislow,thecounterwillbeclearedwhenacomparematchoccursfrom theComparatorPorwithacounteroverflow.Acounteroverflowclearingmethodcan onlybeimplementediftheCCRPbitsareallclearedtozero.TheSTnCCLRbitisnot usedinthePWMOutput,SinglePulseOutputorCaptureInputMode. |
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