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HT66F4530 Datasheet(PDF) 31 Page - Holtek Semiconductor Inc |
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HT66F4530 Datasheet(HTML) 31 Page - Holtek Semiconductor Inc |
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31 / 224 page  Rev. 1.00 30 De�e��e� �1� �01� Rev. 1.00 31 De�e��e� �1� �01� HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers HT66F4530/HT66F4540/HT66F4550 A/D Flash MCU with Dual Operational Amplifiers System Architecture Akeyfactorinthehigh-performancefeaturesoftheHoltekrangeofmicrocontrollersisattributed totheirinternalsystemarchitecture.Therangeofthesedevicestakeadvantageoftheusual featuresfoundwithinRISCmicrocontrollersprovidingincreasedspeedofoperationandenhanced performance.Thepipeliningschemeisimplementedinsuchawaythatinstructionfetchingand instructionexecutionareoverlapped,henceinstructionsareeffectivelyexecutedinoneortwocycles formostofthestandardorextendedinstructionsrespectively.Theexceptionstothisarebranchor callinstructionswhichneedonemorecycle.An8-bitwideALUisusedinpracticallyallinstruction setoperations,whichcarriesoutarithmeticoperations,logicoperations,rotation,increment, decrement,branchdecisions,etc.Theinternaldatapathissimplifiedbymovingdatathroughthe AccumulatorandtheALU.CertaininternalregistersareimplementedintheDataMemoryand canbedirectlyorindirectlyaddressed.Thesimpleaddressingmethodsoftheseregistersalong withadditionalarchitecturalfeaturesensurethataminimumofexternalcomponentsisrequired toprovideafunctionalI/OandA/Dcontrolsystemwithmaximumreliabilityandflexibility.This makesthesedevicessuitableforlow-cost,high-volumeproductionforcontrollerapplications. Clocking and Pipelining Themainsystemclock,derivedfromeitheraHXT,LXT,HIRCorLIRCoscillatorissubdivided intofourinternallygeneratednon-overlappingclocks,T1~T4.TheProgramCounterisincremented atthebeginningoftheT1clockduringwhichtimeanewinstructionisfetched.Theremaining T2~T4clockscarryoutthedecodingandexecutionfunctions.Inthisway,oneT1~T4clock cycleformsoneinstructioncycle.Althoughthefetchingandexecutionofinstructionstakesplace inconsecutiveinstructioncycles,thepipeliningstructureofthemicrocontrollerensuresthat instructionsareeffectivelyexecutedinoneinstructioncycle.Theexceptiontothisareinstructions wherethecontentsoftheProgramCounterarechanged,suchassubroutinecallsorjumps,inwhich casetheinstructionwilltakeonemoreinstructioncycletoexecute. Fet�h Inst. (PC+�) Exe�ute Inst. (PC+1) Os�illato� Clo�k (Syste� Clo�k) Phase Clo�k T1 Phase Clo�k T� Phase Clo�k T3 Phase Clo�k T4 P�og�a� Counte� Pipelining PC PC+1 PC+� Fet�h Inst. (PC+1) Exe�ute Inst. (PC) Exe�ute Inst. (PC-1) Fet�h Inst. (PC) System Clocking and Pipelining Forinstructionsinvolvingbranches,suchasjumporcallinstructions,twomachinecyclesare requiredtocompleteinstructionexecution.Anextracycleisrequiredastheprogramtakesone cycletofirstobtaintheactualjumporcalladdressandthenanothercycletoactuallyexecutethe branch.Therequirementforthisextracycleshouldbetakenintoaccountbyprogrammersintiming sensitiveapplications. |
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