PI7C9X760ACLEX datasheet(14/53 Pages) DIODES

14 / 53 page

www.diodes.com

April 2019

Diodes Incorporated

PI7C9X760

Document Number DS40305 Rev 6-2

A product Line of

Diodes Incorporated

PI7C9X760

6 Sleep mode

Sleep mode is an enhanced feature of the UART. It is enabled when EFR[4], the enhanced functions bit, is set and when IER[4] is set.

Sleep mode is entered when:

• The serial data input line, RX, is idle (see Section 7 “Break and time-out conditions”).

• The TX FIFO and TX shift register are empty.

• There are no interrupts pending except THR.

Remark: Sleep mode will not be entered if there is data in the RX FIFO.

In Sleep mode, the clock to the UART is stopped. Since most registers are clocked using these clocks, the power consumption is greatly

reduced. The UART will wake up when any change is detected on the RX line, when there is any change in the state of the modem

input pins, or if data is written to the TX FIFO.

Remark: Writing to the divisor latches DLL and DLH to set the baud clock must not be done during Sleep mode. Therefore, it is advis-

able to disable Sleep mode using IER[4] before writing to DLL or DLH.

7 Break and time-out conditions

When the UART receives a number of characters and these data are not enough to set off the receive interrupt (because they do not

reach the receive trigger level), the UART will generate a time-out interrupt instead, 4 character times after the last character is re-

ceived. The time-out counter will be reset at the center of each stop bit received or each time the receive FIFO is read.

A break condition is detected when the RX pin is pulled LOW for a duration longer than the time it takes to send a complete character

plus start, stop and parity bits. A break condition can be sent by setting LCR[6], when this happens the TX pin will be pulled LOW

until LSR[6] is cleared by the software.

8 Programmable baud rate generator

The UART contains a programmable baud rate generator that takes any clock input and divides it by a divisor in the range between 1

and (216 - 1). An additional divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in Figure 7. The formula

for the baud rate is:

Where:

prescaler = 1, when MCR[7] is set to logic 0 after reset (divide-by-1 clock selected)

prescaler = 4, when MCR[7] is set to logic 1 after reset (divide-by-4 clock selected).

Divisor = {DLH, DLL}

Sample rate = 16 - SCR + CPRN

Remark: The default value of prescaler after reset is divide-by-1.

rate

sample

divisor

)

prescaler

frequency

input

crystal

XTAL1

(

rate

Baud

PI7C9X760ACLEX Datasheet(PDF) 14 Page - Diodes Incorporated

PI7C9X760ACLEX Datasheet(HTML) 14 Page - Diodes Incorporated

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

Datasheet Download

Link URL