PI7C9X760ACLEX datasheet(26/53 Pages) DIODES

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April 2019

Diodes Incorporated

PI7C9X760

Document Number DS40305 Rev 6-2

A product Line of

Diodes Incorporated

PI7C9X760

Configuration Registers

Offset 00H: Receiver Holding Register (RHR). Accessible when LCR[7]=0. Default=00

Bit

Type

Description

[7:0]

Rx Holding - When data are read from the RHR,they are removed from the top of the receiver's FIFO.

Data read from the RHR when FIFO is empty are invalid. The Line Status Register(LSR) indicates the

full or empty status of the FIFOs.

Offset 00H: Transmitter Holding Register (THR). Accessible when LCR[7]=0. Default=00

Bit

Type

Description

[7:0]

Tx Holding - When data are written to the THR,they are written to the bottom of the transmitter's

FIFO. Data written to the THR when FIFO is full are lost. The Line Status Register(LSR) indicates the

full or empty status of the FIFOs.

Offset 00H: Divisor Latch LSB(DLL). Accessible when LCR[7]=1 and LCR!=0xBF. Default=01

Bit

Type

Description

[7:0]

LSB bits of divisor for baud rate generator.

Note: It is reset only when Power-On-Reset.

Offset 01H: Interrupt Enable Register (IER). Accessible when LCR[7]=0. Default=00

Bit

Type

Description

CTS interrupt - "1": Enable CTS/DSR interrupt

RTS interrupt - "1": Enable RTS/DTR interrupt

Xoff/Special character interrupt - "1": Enable the Software Flow Control interrupt

Sleep mode - "1" : Enable sleep mode (It requires EFR[4] = 1). The UART may enter sleep mode when

all conditions met:

- no interrupts pending

- modem inputs are not toggled

- RX input pin is idling HIGH

- TX/RX FIFO are empty

It will exit from sleep mode when any below condition met:

- modem inputs are toggling

- RX input pin changed to LOW

-a data byte is loaded to the TX FIFO

In sleep mode, Crystal is stopped and no UART clock

Modem Status interrupt - "1": Enable Modem Status interrupt

Receiver Line Status interrupt - "1": Enable Receiver Line Status interrupt

Tx Ready interrupt - "1": Enable THR Ready interrupt

1 = Interrupt is issued whenever the THR becomes empty in non-FIFO mode or when spaces in the

FIFO is above the trigger level in the FIFO mode.

Rx Data Ready interrupt - "1": enable Data Ready interrupt

Note: IER[7:4] can only be modified if EFR[4]=1.

PI7C9X760ACLEX Datasheet(PDF) 26 Page - Diodes Incorporated

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