PI7C9X760ACLEX datasheet(30/53 Pages) DIODES

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www.diodes.com

April 2019

Diodes Incorporated

PI7C9X760

Document Number DS40305 Rev 6-2

A product Line of

Diodes Incorporated

PI7C9X760

Offset 04H: XON1 character Register (XON1). Accessible when LCR=0xBF and SFR[2]=0. Default=00

Bit

Type

Description

[7:0]

XON1 character

Note: It is reset only when Power-On-Reset.

Offset 05H: Line Status Register (LSR). Accessible when LCR[7]=0. Default=60

Bit

Type

Description

Receiver FIFO Data Error Flag.

0 = No FIFO Error

1 = a flag for the sum of all error bits (parity error, framing error, or break) in the RX FIFO. This bit

clears when there is no more error in any of the bytes in the RX FIFO.

THR and TSR Empty Flag

This bit is set whenever the transmitter goes idle, it clears whenever either the THR or TSR contains a

data character.

THR Empty Flag

This bit is set when the last data byte is transferred from THR to TSR.

Receiver Break Error Flag

0 = No Break Error

1 = break condition occurred in data to be read from RX FIFO(RX was LOW for at least one character

frame time).

Receiver Data Framing Error Flag

0 = No Data Framing Error

1 = framing error occurred in data to be read from RX FIFO (The receive character did not have a

valid stop bits).

Receiver Data Parity Error Flag

0 = No Data Parity Error

1 = parity error in data to be read from RX FIFO

Receiver Overrun Error

0 = No overrun Error

1 = additional data received while the RX FIFO is full. This data should not be transferred into FIFO.

Receiver Data Ready Indicator

0 = No data in received in RX FIFO

1 = Data has been received and saved in the RX FIFO

Offset 05H: XON2 character Register (XON2). Accessible when LCR=0xBF and SFR[2]=0. Default=00

Bit

Type

Description

[7:0]

XON2 character

Note: It is reset only when Power-On-Reset.

Offset 06H: Modem Status Register (MSR). Accessible when LCR[7]=0 and MCR[2]=0 and SFR[2]=0. Default=00

Bit

Type

Description

CD input status

Normally this bit is the complement of the CD# input.

In the loopback mode this bit is equivalent to MCR[3].

Configuration Registers cont..

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