UPD75P3018A datasheet(41/66 Pages) RENESAS

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µPD75P3018A

Data Sheet U11917EJ2V1DS

AC Characteristics (TA = –40 to +85

°C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle time Note 1

tCY

Operation with

VDD = 2.7 to 5.5 V

0.67

µs

(minimum instruction execution

main system clock

0.95

µs

time = 1 machine cycle)

Operation with subsystem clock

114

122

125

µs

TI0, TI1, TI2 input frequency

fTI

VDD = 2.7 to 5.5 V

1.0

MHz

275

kHz

TI0, TI1, TI2 input high-/

tTIH, tTIL

VDD = 2.7 to 5.5 V

0.48

µs

low-level width

1.8

µs

Interrupt input high-/low-level tINTH, tINTL INT0

IM02 = 0

Note 2

µs

width

IM02 = 1

µs

INT1, 2, 4

µs

KR0-7

µs

RESET low-level width

tRSL

µs

Notes 1. The cycle time (minimum instruc-

tion execution time) of the CPU

clock (

Φ) is determined by the

oscillation frequency of the

connected

resonator

(and

external clock), the system clock

control register (SCC), and

processor clock control register

(PCC).

The figure on the right shows the

supply voltage VDD vs. cycle time

tCY characteristics when the

device operates with the main

system clock.

2. 2tCY or 128/fX depending on the

setting of the interrupt mode

Operation

guaranteed range

Supply voltage

VDD [V]

0123456

0.5

tCY vs VDD

(with main system clock)

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