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UPD75P3018A Datasheet(PDF) 14 Page - Renesas Technology Corp |
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UPD75P3018A Datasheet(HTML) 14 Page - Renesas Technology Corp |
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14 / 66 page  µPD75P3018A 12 Data Sheet U11917EJ2V1DS 3.4 Recommended Connection for Unused Pins Pin Recommended Connection P00/INT4 Connect to VSS or VDD P01/SCK Connect to VSS or VDD via a resistor individually P02/SO/SB0 P03/SI/SB1 Connect to VSS P10/INT0, P11/INT1 Connect to VSS or VDD P12/TI1/TI2/INT2 P13/TI0 P20/PTO0 Input : Connect to VSS or VDD via a resistor individually P21/PTO1 Output : Leave open P22/PTO2/PCL P23/BUZ P30/LCDCL/MD0 P31/SYNC/MD1 P32/MD2, P33/MD3 P40/D0-P43/D3 Connect to VSS P50/D4-P53/D7 P60/KR0-P63/KR3 Input : Connect to VSS or VDD via a resistor individually P70/KR4-P73/KR7 Output : Leave open S0-S23 Leave open S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 Connect to VSS BIAS Connect to VSS only when VLC0 to VLC2 are all not used. In other cases, leave open. XT1Note Connect to VSS XT2Note Leave open Note When subsystem clock is not used, specify SOS.0 = 1 (indicates that internal feedback resistor is disconnected). |
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