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AMD-K6-2E/233AMZ Datasheet(PDF) 165 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ Datasheet(HTML) 165 Page - Advanced Micro Devices |
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165 / 332 page  Chapter 6 Bus Cycles 147 22529B/0—January 2000 AMD-K6™-2E Processor Data Sheet Preliminary Information Misaligned I/O Read and Write Table 26 shows the misaligned I/O read and write cycle order executed by the AMD-K6-2E processor. In Figure 57, the least-significant bytes (LSBs) are transferred first. Immediately after the processor samples BRDY# asserted, it drives the second bus cycle to transfer the most-significant bytes (MSBs) to complete the misaligned bus cycle. Figure 57. Misaligned I/O Transfer Table 26. Bus-Cycle Order During Misaligned I/O Transfers Type of Access First Cycle Second Cycle I/O Read LSBs MSBs I/O Write LSBs MSBs LSB MSB LSB MSB Misaligned I/O Read Misaligned I/O Write CLK A[31:3] BE[7:0]# ADS# M/IO# D/C# W/R# D[63:0] BRDY# ADDR DATA DATA IDLE ADDR DATA DATA IDLE ADDR DATA DATA DATA IDLE ADDR DATA DATA DATA IDLE SCYC |
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