AMD-K6-2ESLASH233AMZ datasheet(227/332 Pages) AMD

227 / 332 page

Chapter 9

Write Merge Buffer

209

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

WCn (n=0, 1). When set to 1, this memory range is defined as

write combinable (see Table 38 on page 209). Write-combinable

memory is uncacheable.

UCn (n=0, 1). When set to 1, this memory range is defined as

uncacheable (see Table 38).

9.3

Memory-Range Restrictions

The following rules regarding the address alignment and size of

each range must be adhered to when programming the physical

base address and physical address mask fields of the UWCCR

The minimum size of each range is 128 Kbytes.

The physical base address must be aligned on a 128-Kbyte

boundary.

The physical base address must be range-size aligned. For

example, if the size of the range is 1 Mbyte, then the

physical base address must be aligned on a 1-Mbyte

boundary.

All bits set to 1 in the physical address mask must be

contiguous. Likewise, all bits cleared to 0 in the physical

address mask must be contiguous. For example:

111_1111_1100_0000b is a valid physical address mask

111_1111_1101_0000b is invalid

Table 38. WC/UC Memory Type

WCn

UCn

Memory Type

No effect on cacheability or write combining

Write-combining memory range (uncacheable)

0 or 1

Uncacheable memory range

AMD-K6-2E/233AMZ Datasheet(PDF) 227 Page - Advanced Micro Devices