AMD-K6-2ESLASH233AMZ datasheet(231/332 Pages) AMD

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Chapter 10

Floating-Point and Multimedia Execution Units

213

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Floating-Point and Multimedia Execution Units

10.1

Floating-Point Execution Unit

The AMD-K6-2E processor contains an IEEE 754-compatible

and IEEE 854-compatible floating-point execution unit

designed to accelerate the performance of software that utilizes

the x86 floating-point instruction set. Floating-point software is

typically written to manipulate numbers that are very large or

very small, that require a high degree of precision, or that result

fr om

c o mple x

mat h em atical

oper ations

suc h

a s

transce ndentals. Applic ations t hat t a ke adva ntage of

floating-point operations include geometric calculations for

graphics acceleration, scientific, statistical, and engineering

applications, and business applications that use large amounts

of high-precision data.

The high-performance floating-point execution unit contains an

adder unit, a multiplier unit, and a divide/square root unit.

These low-latency units can execute floating-point instructions

in as few as two processor clocks. To increase performance, the

proce sso r is de sig n ed to simu l ta n eo usly de code mo st

floating-point instructions with most short-decodeable

instructions.

See “Software Environment” on page 23 for a description of the

floating-point data types, registers, and instructions.

Handling

Floating-Point

Exceptions

The AMD-K6-2E processor provides the following two types of

exception handling for floating-point exceptions:

If the numeric error (NE) bit in CR0 is 1, the processor

invokes the interrupt 10h handler. In this manner, the

floating-point exception is completely handled by software.

If the NE bit in CR0 is 0, the processor requires external

logic to generate an interrupt on the INTR signal in order to

handle the exception.

External Logic

Support of

Floating-Point

Exceptions

The processor provides the FERR# (Floating-Point Error) and

IGNNE# (Ignore Numeric Error) signals to allow the external

logic to generate the interrupt in a manner consistent with

PC/AT-compatible systems. The assertion of FERR# indicates

the occurrence of an unmasked floating-point exception

resulting from the execution of a floating-point instruction.

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