AMD-K6-2ESLASH233AMZ datasheet(253/332 Pages) AMD

253 / 332 page

Chapter 12

Test and Debug

235

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Bypass Register (BR). The BR is a Test Data register consisting of a

1-bit shift register that provides the shortest path between TDI

and TD O. When the processor is not involved in a test

operation, the BR can be selected by an instruction to allow the

transfer of test data through the processor without having to

serially scan the test data through the BSR. This functionality

preserves the state of the BSR and significantly reduces test

time.

The BR register is selected by the BYPASS and HIGHZ

instructions as well as by any instructions not supported by the

AMD-K6-2E processor.

TAP Instructions

The processor supports the three instructions required by the

IEEE 1149.1 standard — EXTEST, SAMPLE/PRELOAD, and

BYPASS — as well as two additional optional instructions —

IDCODE and HIGHZ.

Table 47 shows the complete set of TAP instructions supported

by the processor along with the 5-bit Instruction Register

encoding and the register selected by each instruction.

EXTEST Instruction. When the EXTEST instruction is executed,

the processor loads the BSR shift register with the current state

of the input and bidirectional pins in the Capture-DR state and

drives the output and bidirectional pins with the corresponding

values from the BSR output register in the Update-DR state.

Table 47. Supported Test Access Port (TAP) Instructions

Instruction

Encoding

Description

EXTEST1

00000b

BSR

Sample inputs and drive outputs

SAMPLE / PRELOAD

00001b

BSR

Sample inputs and outputs, then load the BSR

IDCODE

00010b

DIR

Read DIR

HIGHZ

00011b

Float outputs and bidirectional pins

BYPASS2

00100b–11110b

Undefined instruction, execute the BYPASS instruction

BYPASS3

11111b

Connect TDI to TDO to bypass the BSR

Notes:

1. Following the execution of the EXTEST instruction, the processor must be reset to return to normal, non-test operation.

2. These instruction encodings are undefined on the AMD-K6-2E processor and default to the BYPASS instruction.

3. Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open

during an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.

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