AMD-K6-2ESLASH233AMZ datasheet(249/332 Pages) AMD

249 / 332 page

Chapter 12

Test and Debug

231

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

TAP Registers

The AMD-K6-2E processor provides an Instruction register (IR)

and thr e e Te st Data register s (TD R ) to su pport the

boundary-scan architecture. The IR and one of the TDRs —the

Boundary-Scan register (BSR) — consist of a shift register and

an output register. The shift register is loaded in parallel in the

Capture states. (See “TAP Controller State Machine” on page

236 for a description of the TAP controller states.) In addition,

the shift register is loaded and shifted serially in the Shift

states. The output register is loaded in parallel from its

corresponding shift register in the Update states.

Instruction Register (IR). The IR is a 5-bit register, without parity,

that determines which instruction to run and which test data

Capture-IR state, the processor loads the following bits into the

IR shift register:

01b—Loaded into the two least significant bits, as specified

by the IEEE 1149.1 standard

000b—Loaded into the three most significant bits

Loading 00001b into the IR shift register during the Capture-IR

state results in loading the SAMPLE/PRELOAD instruction.

For each entry into the Shift-IR state, the IR shift register is

serially shifted by one bit toward the TDO pin. During the shift,

the most significant bit of the IR shift register is loaded from

the TDI pin.

The IR output register is loaded from the IR shift register in the

Update-IR state, and the current instruction is defined by the IR

output register. See “TAP Instructions” on page 235 for a list and

definition of the instructions supported by the AMD-K6-2E

processor.

Boundary Scan Register (BSR). The Boundary Scan Register is a Test

Da ta reg ister consisting o f the inte rconnection of 152

boundary-scan cells. Each output and bidirectional pin of the

processor requires a two-bit cell, where one bit corresponds to

the pin and the other bit is the output enable for the pin. When

a 0 is shifted into the enable bit of a cell, the corresponding pin

is floated, and when a 1 is shifted into the enable bit, the pin is

driven valid. Each input pin requires a one-bit cell that

corresponds to the pin. The last cell of the BSR is reserved and

does not correspond to any processor pin.

AMD-K6-2E/233AMZ Datasheet(PDF) 249 Page - Advanced Micro Devices

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