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AMD-K6-2E/233AMZ Datasheet(PDF) 246 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ Datasheet(HTML) 246 Page - Advanced Micro Devices |
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246 / 332 page ![]() 228 Test and Debug Chapter 12 AMD-K6™-2E Processor Data Sheet 22529B/0—January 2000 Preliminary Information 12.2 Three-State Test Mode The three-state test mode causes the processor to float its output and bidirectional pins, which is useful for board-level manu fa c turing t e sting . I n t h is m o de, t he proc esso r is electrically isolated from other components on a system board, allowing automated test equipment (ATE) to test components that drive the same signals as those the processor floats. If the FLUSH# signal is sampled Low during the falling transition of RESET, the processor enters the three-state test mode. (See “FLUSH# (Cache Flush)” on page 104 for the specific sampling requirements.) The signals floated in the three-state test mode are as follows: The VCC2DET, VCC2H/L#, and TDO signals are the only outputs not floated in the three-state test mode. s VCC2DET and VCC2H/L# must remain Low to ensure the system continues to supply the specified processor core voltage to the VCC2 pins. s TDO is never floated because the boundary-scan Test Access Port must remain enabled at all times, including during the three-state test mode. The three-state test mode is exited when the processor samples RESET asserted. s A[31:3] s D/C# s M/IO# s ADS# s D[63:0] s PCD s ADSC# s DP[7:0] s PCHK# s AP s FERR# s PWT s APCHK# s HIT# s SCYC s BE[7:0]# s HITM# s SMIACT# s BREQ s HLDA s W/R# s CACHE# s LOCK# |
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