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AMD-K6-2E/233AMZ Datasheet(PDF) 243 Page - Advanced Micro Devices |
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AMD-K6-2E/233AMZ Datasheet(HTML) 243 Page - Advanced Micro Devices |
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243 / 332 page ![]() Chapter 11 System Management Mode (SMM) 225 22529B/0—January 2000 AMD-K6™-2E Processor Data Sheet Preliminary Information Table 44 shows the format of the I/O trap restart slot. The processor initializes the I/O trap restart slot to 0000h upon entry into SMM. If SMM was entered due to a trapped I/O instruction, the processor indicates the validity of the I/O instruction by se tti ng or cleari ng bit 1 of the I/O trap doubleword at offset FFA4h in the SMM state-save area. The SM M s e rv i c e ro uti n e s h o u l d te st bi t 1 o f th e I /O trap doubleword to determine if a valid I/O instruction was being executed when entering SMM and before writing the I/O trap restart slot. If the I/O instruction is valid, the SMM service routine can safely rewrite the I/O trap restart slot with the value 00FFh, which causes the processor to re-execute the trapped I/O instruction when the RSM instruction is executed. If the I/O instruction is invalid, writing the I/O trap restart slot has undefined results. If a second SMI# is asserted and a valid I/O instruction was trapped by the first SMM handler, the CPU services the second SMI# prior to re-executing the trapped I/O instruction. The second entry into SMM neve r has bit 1 of th e I/O trap doubleword set, and the second SMM service routine must not rewrite the I/O trap restart slot. During a simultaneous SMI# I/O instruction trap and debug breakpoint trap, the AMD-K6-2E processor first responds to the SMI# and postpones recognizing the debug exception until after returning from SMM via the RSM instruction. If the debug registers DR3–DR0 are used while in SMM, they must be saved and restored by the SMM handler. The processor automatically saves and restores DR7–DR6. If the I/O trap restart slot in the SMM state-save area contains the value 00FFh when the RSM instruction is executed, the debug trap does not occur until after the I/O instruction is re-executed. Table 44. I/O Trap Restart Slot 31–16 15–0 Reserved I/O Instruction restart on return from SMM: s 0000h = Execute the next instruction after the trapped I/O s 00FFh = Re-execute the trapped I/O instruction |
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