AMD-K6-2ESLASH233AMZ datasheet(241/332 Pages) AMD

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Chapter 11

System Management Mode (SMM)

223

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Upon entry into SMM, the halt restart slot is defined as follows:

Bits 15–1—Reserved

Bit 0—Point of entry to SMM:

1 = entered from Halt state

0 = not entered from Halt state

After entry into the SMI handler and before returning from

SMM, the halt restart slot can be written using the following

definition:

Bits 15–1—Reserved

Bit 0—Point of return when exiting from SMM:

1 = return to Halt state

0 = return to next instruction after the HLT instruction

If the return from SMM takes the processor back to the Halt

state, the HLT instruction is not re-executed, but the Halt

special bus cycle is driven on the bus after the return.

11.6

I/O Trap Doubleword

If the assertion of SMI# is recognized during the execution of an

I/O instruction, the I/O trap doubleword at offset FFA4h in the

SMM st at e-save area c o nt ains info rm at ion ab o u t the

instruction. The fields of the I/O trap doubleword are

configured as follows:

Bits 31–16—I/O port address

Bits 15–4—Reserved

Bit 3—REP (repeat) string operation (1 = REP string, 0 = not

a REP string)

Bit 2—I/O string operation (1 = I/O string, 0 = not a I/O

string)

Bit 1—Valid I/O instruction (1 = valid, 0 = invalid)

Bit 0—Input or output instruction (1 = INx, 0 = OUTx)

AMD-K6-2E/233AMZ Datasheet(PDF) 241 Page - Advanced Micro Devices