AMD-K6-2ESLASH233AMZ datasheet(237/332 Pages) AMD

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Chapter 11

System Management Mode (SMM)

219

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Table 40 shows the initial state of registers when entering SMM.

11.2

SMM State-Save Area

When the processor acknowledges an SMI# interrupt by

asserting SMIACT#, it saves its state in a 512-byte SMM

state-save area shown in Table 41. The save begins at the top of

the SMM memory area (SMM base address + FFFFh) and fills

down to SMM base address + FE00h.

Table 41 shows the offsets in the SMM state-save area relative

to the SMM base address. The SMM service routine can alter

any of the read/write values in the state-save area.

Table 40. Initial State of Registers in System Management Mode (SMM)

SMM Initial State

General-Purpose Registers

Unmodified

EFLAGs

0000_0002h

CR0

PE, EM, TS, and PG are cleared (bits 0, 2, 3, and 31).

The other bits are unmodified.

DR7

0000_0400h

GDTR, LDTR, IDTR, TSSR, DR6 Unmodified

EIP

0000_8000h

0003_0000h

DS, ES, FS, GS, SS

0000_0000h

Table 41. SMM State-Save Area Map

Address Offset

Contents Saved

FFFCh

CR0

FFF8h

CR3

FFF4h

EFLAGS

FFF0h

EIP

FFECh

EDI

FFE8h

ESI

FFE4h

EBP

FFE0h

ESP

FFDCh

EBX

FFD8h

EDX

FFD4h

ECX

FFD0h

EAX

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