AMD-K6-2ESLASH233AMZ datasheet(247/332 Pages) AMD

247 / 332 page

Chapter 12

Test and Debug

229

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

12.3

Boundary-Scan Test Access Port (TAP)

The boundary-scan Test Access Port (TAP) is an IEEE standard

that defines synchronous scanning test methods for complex

logic circuits, such as boards containing a processor. The

AMD-K6-2E processor supports the TAP standard defined in

th e I EEE Standard Te st Acces s Po rt and Bo undary-Scan

Architecture (IEEE 1149.1-1990) specification.

Boundary scan testing uses a shift register consisting of the

serial interconnection of boundary-scan cells that correspond to

each I/O buffer of the processor. This non-inverting register

chain, called a Boundary Scan register (BSR), can be used to

capture the state of every processor pin and to drive every

processor output and bidirectional pin to a known state.

Each BSR of every component on a board that implements the

boundary-scan architecture can be serially interconnected to

enable component interconnect testing.

Test Access Port

The Test Access Port (TAP) consists of the following:

Test Access Port (TAP) Controller—The TAP controller is a

synchronous, finite state machine that uses the TMS and

TDI input signals to control a sequence of test operations.

See “TAP Controller State Machine” on page 236 for a list

of TAP states and their definition.

Instruction Register (IR)—The IR contains the instructions

that select the test operation to be performed and the Test

Data Register (TDR) to be selected. See “TAP Registers” on

page 231 for more details on the IR.

Test Data Registers (TDR)—The three TDRs are used to

process the test data. Each TDR is selected by an

instruction in the Instruction Register (IR). See “TAP

Registers” on page 231 for a list of these registers and their

functions.

AMD-K6-2E/233AMZ Datasheet(PDF) 247 Page - Advanced Micro Devices