| Electronic Components Datasheet Search |
|
AMD-K6-2E/233AMZ Datasheet(PDF) 287 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AMD-K6-2E/233AMZ Datasheet(HTML) 287 Page - Advanced Micro Devices |
|
287 / 332 page ![]() Chapter 15 Signal Switching Characteristics 269 22529B/0—January 2000 AMD-K6™-2E Processor Data Sheet Preliminary Information Figure 89. CLK Waveform 15.4 Valid Delay, Float, Setup, and Hold Timings Valid Delay and Float Timing The maximum valid delay timings are provided to allow a system designer to determine if setup times to the system logic can be met. Likewise, the minimum valid delay timings are used to analyze hold times to the system logic. s Valid delay and float timings are given for output signals during functional operation and are given relative to the rising edge of CLK. s During boundary-scan testing, valid delay and float timings for output signals are with respect to the falling edge of TCK. Setup and Hold Timing The setup and hold time requirements for the AMD-K6-2E processor input signals must be met by the system logic to assure the proper operation of the processor. s The setup and hold timings during functional and boundary-scan test mode are given relative to the rising edge of CLK and TCK, respectively. t5 2.0 V 1.5 V 0.8 V t2 t3 t4 t1 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |