AMD-K6-2ESLASH233AMZ datasheet(285/332 Pages) AMD

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Chapter 15

Signal Switching Characteristics

267

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

Signal Switching Characteristics

The AMD-K6-2E processor signal switching characteristics are

presented in tables 56 through 65. Valid delay, float, setup, and

hold timing specifications are listed. These specifications are

provided for the system designer to determine if the timings

necessary for the processor to interface with the system logic

are met.

Table 56 and Table 57 on page 268 contain the switching

characteristics of the CLK input.

Table 58 through Table 61, beginning on page 270, contain

the timings for the normal operation signals.

Table 62 on page 278 and Table 63 on page 279 contain the

timings for RESET and the configuration signals.

Table 64 and Table 65 on page 280 contain the timings for

the test operation signals.

All signal timings provided are:

Measured between CLK, TCK, or RESET at 1.5 V and the

corresponding signal at 1.5 V—this applies to input and

output signals that are switching from Low to High, or from

High to Low

Based on input signals applied at a slew rate of 1 V/ns

between 0 V and 3 V (rising) and 3 V to 0 V (falling)

Valid within the operating ranges given in “Operating

Ranges” on page 254

Based on a load capacitance (CL) of 0 pF

15.1

CLK Switching Characteristics

Table 56 and Table 57 contain the switching characteristics of

the CLK input to the AMD-K6-2E processor for 100-MHz and

66-MHz bus operation, respectively, as measured at the voltage

levels indicated by Figure 89 on page 269.

The CLK Period Stability parameter specifies the variance

(jitter) allowed between successive periods of the CLK input

measured at 1.5 V. This parameter must be considered as one of

the elements of clock skew between the AMD-K6-2E and the

system logic.

AMD-K6-2E/233AMZ Datasheet(PDF) 285 Page - Advanced Micro Devices

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