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AMD-K6-2E/233AMZ Datasheet(PDF) 282 Page - Advanced Micro Devices

Part # AMD-K6-2E/233AMZ
Description  AMD-K6??2E Embedded Processor
PDF  332 Pages
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Manufacturer  AMD [Advanced Micro Devices]
Direct Link  http://www.amd.com
Logo AMD - Advanced Micro Devices

AMD-K6-2E/233AMZ Datasheet(HTML) 282 Page - Advanced Micro Devices

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Electrical Data
Chapter 14
AMD-K6™-2E Processor Data Sheet
22529B/0—January 2000
Preliminary Information
Pin Connection
Requirements
For proper operation, the following requirements for signal pin
connections must be met:
s
Do not drive address and data signals into large capacitive
loads at high frequencies. If necessary, use buffer chips to
drive large capacitive loads.
s
Leave all NC (no-connect) pins unconnected.
s
Unused
inputs
should
always
be
connected
to
an
appropriate signal level.
•
Active Low inputs that are not being used should be
connected to VCC3 through a 20-kW pullup resistor.
•
Active High inputs that are not being used should be
connected to GND through a pulldown resistor.
s
Reserved signals can be treated in one of the following ways:
•
As no-connect (NC) pins, in which case these pins are left
unconnected
•
As pins connected to the system logic as defined by the
industry-standard Socket 7 and Super7 interfaces
•
Any combination of NC and Socket 7 pins
s
Keep trace lengths to a minimum.
14.7
I/O Buffer Characteristics
All of the AMD-K6-2 E process o r inputs , outputs, and
bidirectional buffers are implemented using a 3.3 V buffer
design. AMD has developed a model that represents the
characteristics of the actual I/O buffer to allow system
designers to perform analog simulations of AMD-K6-2E
processor signals that interface with the system logic. Analog
simulations are used to determine a signal’s time of flight from
source to destination and to ensure that the system’s signal
quality requirements are met. Signal quality measurements
include overshoot, undershoot, slope reversal, and ringing.
I/O Buffer Model
AMD provides a model of the AMD-K6-2E processor I/O buffer
for system designers to use in board-level simulations. This I/O
buf f er m o del conform s to the I/O Buffe r In forma t ion
Specification (IBIS). The I/O model contains voltage versus
current (V/I) and voltage versus time (V/T) data tables for
accurate modeling of I/O buffer behavior.



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