AMD-K6-2ESLASH233AMZ datasheet(123/332 Pages) AMD

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Chapter 5

Signal Descriptions

105

22529B/0—January 2000

AMD-K6™-2E Processor Data Sheet

Preliminary Information

5.24

HIT# (Inquire Cycle Hit)

Pin Attribute

Output

Pin Location

AK-06

Summary

The processor asserts HIT # during an inquire cycle to indicate

that the cache line is valid within the processor’s instruction or

data cache (also known as a cache hit). The cache line can be in

the modified, exclusive, or shared state.

Driven

HIT # is always driven — except in the three-state test mode —

and only changes state the clock edge after the clock edge on

which EADS# is sampled asserted. It is driven in the same state

until the next inquire cycle.

5.25

HITM# (Inquire Cycle Hit To Modified Line)

Pin Attribute

Output

Pin Location

AL-05

Summary

The processor asserts HITM # during an inquire cycle to

indicate that the cache line exists in the processor’s data cache

in the modified state. The processor performs a writeback cycle

as a result of this cache hit. If an inquire cycle hits a cache line

that is currently being written back, the processor asserts

HITM # but does not execute another writeback cycle. The

system logic must not expect the processor to assert ADS# each

time HITM# is asserted.

Driven

HITM# is always driven—except in the three-state test mode—

and, in particular, is driven to represent the result of an inquire

cycle the clock edge after the clock edge on which EADS # is

sampled asserted. If HITM # is negated in response to the

inquire address, it remains negated until the next inquire cycle.

If HITM # is asserted in response to the inquire address, it

remains asserted throughout the writeback cycle and is negated

one clock edge after the last BRDY # of the writeback is

sampled asserted.

AMD-K6-2E/233AMZ Datasheet(PDF) 123 Page - Advanced Micro Devices

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