MC68HC908GR4MP datasheet(227/286 Pages) FREESCALE

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Timebase Register Description

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

227

If the timebase functions are not required during stop mode, reduce the power consumption by stopping

the timebase before enabling the STOP instruction.

21.6 Timebase Register Description

The timebase has one register, the TBCR, which is used to enable the timebase interrupts and set the

rate.

TBIF — Timebase Interrupt Flag

This read-only flag bit is set when the timebase counter has rolled over.

1 = Timebase interrupt pending

0 = Timebase interrupt not pending

TBR2:TBR0 — Timebase Rate Selection

These read/write bits are used to select the rate of timebase interrupts as shown in Table 21-1.

NOTE

Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).

TACK— Timebase ACKnowledge

The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase

interrupt flag bit. Writing a 0 to this bit has no effect.

1 = Clear timebase interrupt flag

0 = No effect

Address:

$001C

Bit 7

654321

Bit 0

Read:

TBIF

TBR2

TBR1

TBR0

TBIE

TBON

Write:

TACK

Reset:

00000000

= Unimplemented

= Reserved

Figure 21-2. Timebase Control Register (TBCR)

Table 21-1. Timebase Rate Selection for OSC1 = 32.768 kHz

TBR2

TBR1

TBR0

Divider

Timebase Interrupt Rate

32,768

1000

8192

250

2048

62.5

128

256

~ 3.9

512

1024

2048

~0.5

4096

~0.24

MC68HC908GR4MP Datasheet(PDF) 227 Page - Freescale Semiconductor, Inc

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