MC68HC908GR4MP datasheet(236/286 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

236

Freescale Semiconductor

cycle generation and removes the ability of the channel to self-correct in the

event of software error or noise. Toggling on output compare also can

cause incorrect PWM signal generation when changing the PWM pulse

width to a new, much larger value.

22.4.4.2 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose output appears on the TCH0 pin.

The TIM channel registers of the linked pair alternately control the pulse width of the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0) links channel 0 and channel 1.

The TIM channel 0 registers initially control the pulse width on the TCH0 pin. Writing to the TIM channel 1

registers enables the TIM channel 1 registers to synchronously control the pulse width at the beginning

of the next PWM period. At each subsequent overflow, the TIM channel registers (0 or 1) that control the

pulse width are the ones written to last. TSC0 controls and monitors the buffered PWM function, and TIM

channel 1 status and control register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,

TCH1, is available as a general-purpose I/O pin.

NOTE

In buffered PWM signal generation, do not write new pulse width values to

the currently active channel registers. User software should track the

currently active channel to prevent writing a new value to the active

channel. Writing to the active channel registers is the same as generating

unbuffered PWM signals.

22.4.4.3 PWM Initialization

To ensure correct operation when generating unbuffered or buffered PWM signals, use the following

initialization procedure:

In the TIM status and control register (TSC):

Stop the TIM counter by setting the TIM stop bit, TSTOP.

Reset the TIM counter and prescaler by setting the TIM reset bit, TRST.

In the TIM counter modulo registers (TMODH:TMODL), write the value for the required PWM

period.

In the TIM channel x registers (TCHxH:TCHxL), write the value for the required pulse width.

In TIM channel x status and control register (TSCx):

Write 0:1 (for unbuffered output compare or PWM signals) or 1:0 (for buffered output compare

or PWM signals) to the mode select bits, MSxB:MSxA. See Table 22-3.

Write 1 to the toggle-on-overflow bit, TOVx.

Write 1:0 (polarity 1 — to clear output on compare) or 1:1 (polarity 0 — to set out on compare)

to the edge/level select bits, ELSxB:ELSxA. The output action on compare must force the

output to the complement of the pulse width level. (See Table 22-3.)

NOTE

In PWM signal generation, do not program the PWM channel to toggle on

output compare. Toggling on output compare prevents reliable 0% duty

cycle generation and removes the ability of the channel to self-correct in the

event of software error or noise. Toggling on output compare can also

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