MC68HC908GR4MP datasheet(238/286 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

238

Freescale Semiconductor

22.7 TIM During Break Interrupts

A break interrupt stops the TIM counter and inhibits input captures.

The system integration module (SIM) controls whether status bits in other modules can be cleared during

the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear

status bits during the break state. See SIM Break Flag Control Register.

To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is

cleared during the break state, it remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),

software can read and write I/O registers during the break state without affecting status bits. Some status

bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the

break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the

second step clears the status bit.

22.8 I/O Signals

Port D shares three of its pins with the TIM. The three TIM channel I/O pins are T1CH0, T1CH1 and

T2CH0 as described in Pin Name Conventions.

Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.

T1CH0 and T2CH0 can be configured as buffered output compare or buffered PWM pins.

22.9 I/O Registers

NOTE

References to either timer 1 or timer 2 may be made in the following text by

omitting the timer number. For example, TSC may generically refer to both

T1SC AND T2SC.

These I/O registers control and monitor operation of the TIM:

•

TIM status and control register (TSC)

•

TIM control registers (TCNTH:TCNTL)

•

TIM counter modulo registers (TMODH:TMODL)

•

TIM channel status and control registers (TSC0, TSC1)

•

TIM channel registers (TCH0H:TCH0L, TCH1H:TCH1L)

22.9.1 TIM Status and Control Register

The TIM status and control register (TSC):

•

Enables TIM overflow interrupts

•

Flags TIM overflows

•

Stops the TIM counter

•

Resets the TIM counter

•

Prescales the TIM counter clock

MC68HC908GR4MP Datasheet(PDF) 238 Page - Freescale Semiconductor, Inc

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