MC68HC908GR4MP datasheet(237/286 Pages) FREESCALE

237 / 286 page

Interrupts

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

237

cause incorrect PWM signal generation when changing the PWM pulse

width to a new, much larger value.

In the TIM status control register (TSC), clear the TIM stop bit, TSTOP.

Setting MS0B links channels 0 and 1 and configures them for buffered PWM operation. The TIM

channel 0 registers (TCH0H:TCH0L) initially control the buffered PWM output. TIM status control

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM overflows. Subsequent output

compares try to force the output to a state it is already in and have no effect. The result is a 0% duty cycle

output.

Setting the channel x maximum duty cycle bit (CHxMAX) and setting the TOVx bit generates a 100% duty

cycle output. (See TIM Channel Status and Control Registers.)

22.5 Interrupts

The following TIM sources can generate interrupt requests:

•

TIM overflow flag (TOF) — The TOF bit is set when the TIM counter reaches the modulo value

programmed in the TIM counter modulo registers. The TIM overflow interrupt enable bit, TOIE,

enables TIM overflow CPU interrupt requests. TOF and TOIE are in the TIM status and control

•

TIM channel flags (CH1F:CH0F) — The CHxF bit is set when an input capture or output compare

occurs on channel x. Channel x TIM CPU interrupt requests are controlled by the channel x

interrupt enable bit, CHxIE. Channel x TIM CPU interrupt requests are enabled when CHxIE = 1.

CHxF and CHxIE are in the TIM channel x status and control register.

22.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power- consumption standby modes.

22.6.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait mode, the TIM registers are not

accessible by the CPU. Any enabled CPU interrupt request from the TIM can bring the MCU out of wait

mode.

If TIM functions are not required during wait mode, reduce power consumption by stopping the TIM before

executing the WAIT instruction.

22.6.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP instruction does not affect

after an external interrupt.

MC68HC908GR4MP Datasheet(PDF) 237 Page - Freescale Semiconductor, Inc