MC68HC908GR4MP datasheet(242/286 Pages) FREESCALE

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Timer Interface Module (TIM)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

242

Freescale Semiconductor

CHxF — Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set when an active edge occurs on

the channel x pin. When channel x is an output compare channel, CHxF is set when the value in the

TIM counter registers matches the value in the TIM channel x registers.

When TIM CPU interrupt requests are enabled (CHxIE = 1), clear CHxF by reading TIM channel x

status and control register with CHxF set and then writing a 0 to CHxF. If another interrupt request

occurs before the clearing sequence is complete, then writing 0 to CHxF has no effect. Therefore, an

interrupt request cannot be lost due to inadvertent clearing of CHxF.

Reset clears the CHxF bit. Writing a 1 to CHxF has no effect.

1 = Input capture or output compare on channel x

0 = No input capture or output compare on channel x

CHxIE — Channel x Interrupt Enable Bit

This read/write bit enables TIM CPU interrupt service requests on channel x.

Reset clears the CHxIE bit.

1 = Channel x CPU interrupt service requests enabled

0 = Channel x CPU interrupt service requests disabled

MSxB — Mode Select Bit B

This read/write bit selects buffered output compare/PWM operation. MSxB exists only in the TIM1

channel 0 and TIM2 channel 0 status and control registers.

Setting MS0B disables the channel 1 status and control register and reverts TCH1 to general-purpose

I/O.

Reset clears the MSxB bit.

1 = Buffered output compare/PWM operation enabled

0 = Buffered output compare/PWM operation disabled

MSxA — Mode Select Bit A

When ELSxB:A

≠ 00, this read/write bit selects either input capture operation or unbuffered output

compare/PWM operation. See Table 22-3.

1 = Unbuffered output compare/PWM operation

0 = Input capture operation

Address:

T1SC0, $0025 and T2SC0, $0030

Bit 7

654321

Bit 0

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

00000000

Figure 22-9. TIM Channel 0 Status and Control Register (TSC0)

Address:

T1SC1, $0028

Bit 7

654321

Bit 0

Read:

CH1F

CH1IE

MS1A

ELS1B

ELS1A

TOV1

CH1MAX

Write:

Reset:

00000000

= Unimplemented

Figure 22-10. TIM Channel 1 Status and Control Register (TSC1)

MC68HC908GR4MP Datasheet(PDF) 242 Page - Freescale Semiconductor, Inc

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