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MC68HC908GR4MP Datasheet(PDF) 107 Page - Freescale Semiconductor, Inc |
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MC68HC908GR4MP Datasheet(HTML) 107 Page - Freescale Semiconductor, Inc |
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107 / 286 page  Opcode Map MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7 Freescale Semiconductor 107 10.7 Opcode Map See Table 10-2. SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X SUB opr,SP SUB opr,SP Subtract A ← (A) – (M) –– IMM DIR EXT IX2 IX1 IX SP1 SP2 A0 B0 C0 D0 E0 F0 9EE0 9ED0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 SWI Software Interrupt PC ← (PC) + 1; Push (PCL) SP ← (SP) – 1; Push (PCH) SP ← (SP) – 1; Push (X) SP ← (SP) – 1; Push (A) SP ← (SP) – 1; Push (CCR) SP ← (SP) – 1; I ← 1 PCH ← Interrupt Vector High Byte PCL ← Interrupt Vector Low Byte ––1– –– INH 83 9 TAP Transfer A to CCR CCR ← (A) INH 84 2 TAX Transfer A to X X ← (A) –––– –– INH 97 1 TPA Transfer CCR to A A ← (CCR) –––– –– INH 85 1 TST opr TSTA TSTX TST opr,X TST ,X TST opr,SP Test for Negative or Zero (A) – $00 or (X) – $00 or (M) – $00 0 – – – DIR INH INH IX1 IX SP1 3D 4D 5D 6D 7D 9E6D dd ff ff 3 1 1 3 2 4 TSX Transfer SP to H:X H:X ← (SP) + 1 –––– –– INH 95 2 TXA Transfer X to A A ← (X) –––– –– INH 9F 1 TXS Transfer H:X to SP (SP) ← (H:X) – 1 –––– –– INH 94 2 WAIT Enable Interrupts; Wait for Interrupt I bit ← 0; Inhibit CPU clocking until interrupted ––0– –– INH 8F 1 A Accumulator n Any bit C Carry/borrow bit opr Operand (one or two bytes) CCR Condition code register PC Program counter dd Direct address of operand PCH Program counter high byte dd rr Direct address of operand and relative offset of branch instruction PCL Program counter low byte DD Direct to direct addressing mode REL Relative addressing mode DIR Direct addressing mode rel Relative program counter offset byte DIX+ Direct to indexed with post increment addressing mode rr Relative program counter offset byte ee ff High and low bytes of offset in indexed, 16-bit offset addressing SP1 Stack pointer, 8-bit offset addressing mode EXT Extended addressing mode SP2 Stack pointer 16-bit offset addressing mode ff Offset byte in indexed, 8-bit offset addressing SP Stack pointer H Half-carry bit U Undefined H Index register high byte V Overflow bit hh ll High and low bytes of operand address in extended addressing X Index register low byte I Interrupt mask Z Zero bit ii Immediate operand byte & Logical AND IMD Immediate source to direct destination addressing mode | Logical OR IMM Immediate addressing mode ⊕ Logical EXCLUSIVE OR INH Inherent addressing mode ( ) Contents of IX Indexed, no offset addressing mode –( ) Negation (two’s complement) IX+ Indexed, no offset, post increment addressing mode # Immediate value IX+D Indexed with post increment to direct addressing mode « Sign extend IX1 Indexed, 8-bit offset addressing mode ← Loaded with IX1+ Indexed, 8-bit offset, post increment addressing mode ? If IX2 Indexed, 16-bit offset addressing mode : Concatenated with M Memory location Set or cleared N Negative bit — Not affected Table 10-1. Instruction Set Summary (Sheet 6 of 6) Source Form Operation Description Effect on CCR VH I N Z C |
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