MC68HC908GR4MP datasheet(166/286 Pages) FREESCALE

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Serial Communications Interface (SCI)

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

166

Freescale Semiconductor

18.4.2.1 Character Length

The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit in SCI control register 1

(SCC1) determines character length. When transmitting 9-bit data, bit T8 in SCI control register 3 (SCC3)

is the ninth bit (bit 8).

18.4.2.2 Character Transmission

During an SCI transmission, the transmit shift register shifts a character out to the PE2/TxD pin. The SCI

data register (SCDR) is the write-only buffer between the internal data bus and the transmit shift register.

To initiate an SCI transmission:

Enable the SCI by writing a 1 to the enable SCI bit (ENSCI) in SCI control register 1 (SCC1).

Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in SCI control register 2

(SCC2).

Clear the SCI transmitter empty bit by first reading SCI status register 1 (SCS1) and then writing

to the SCDR. For 9-bit data, also write the T8 bit in SCC3.

Repeat step 3 for each subsequent transmission.

At the start of a transmission, transmitter control automatically loads the transmit shift register with a

preamble of 1s. After the preamble shifts out, control logic transfers the SCDR data into the transmit shift

A 1 stop bit goes into the most significant bit position.

The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR transfers a byte to the

transmit shift register. The SCTE bit indicates that the SCDR can accept new data from the internal data

bus. If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a

transmitter CPU interrupt request.

When the transmit shift register is not transmitting a character, the PE2/TxD pin goes to the idle condition,

high. If at any time software clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and

receiver relinquish control of the port E pins.

18.4.2.3 Break Characters

Writing a 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with a break character. A

break character contains all 0s and has no start, stop, or parity bit. Break character length depends on

the M bit in SCC1. As long as SBK is at 1, transmitter logic continuously loads break characters into the

transmit shift register. After software clears the SBK bit, the shift register finishes transmitting the last

break character and then transmits at least one 1. The automatic 1 at the end of a break character

guarantees the recognition of the start bit of the next character.

The SCI recognizes a break character when a start bit is followed by eight or nine 0 data bits and a 0

where the stop bit should be.

Receiving a break character has these effects on SCI registers:

•

Sets the framing error bit (FE) in SCS1

•

Sets the SCI receiver full bit (SCRF) in SCS1

•

Clears the SCI data register (SCDR)

•

Clears the R8 bit in SCC3

•

Sets the break flag bit (BKF) in SCS2

•

May set the overrun (OR), noise flag (NF), parity error (PE), or reception in progress flag (RPF) bits

MC68HC908GR4MP Datasheet(PDF) 166 Page - Freescale Semiconductor, Inc

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