MC68HC908GR4MP datasheet(169/286 Pages) FREESCALE

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Functional Description

MC68HC908GR8 • MC68HC908GR4 Data Sheet, Rev. 7

Freescale Semiconductor

169

18.4.3.2 Character Reception

During an SCI reception, the receive shift register shifts characters in from the PE1/RxD pin. The SCI data

After a complete character shifts into the receive shift register, the data portion of the character transfers

to the SCDR. The SCI receiver full bit, SCRF, in SCI status register 1 (SCS1) becomes set, indicating that

the received byte can be read. If the SCI receive interrupt enable bit, SCRIE, in SCC2 is also set, the

SCRF bit generates a receiver CPU interrupt request.

18.4.3.3 Data Sampling

The receiver samples the PE1/RxD pin at the RT clock rate. The RT clock is an internal signal with a

frequency 16 times the baud rate. To adjust for baud rate mismatch, the RT clock is resynchronized at

the following times (see Figure 18-6):

•

After every start bit

•

After the receiver detects a data bit change from 1 to 0 (after the majority of data bit samples at

RT8, RT9, and RT10 returns a valid 1 and the majority of the next RT8, RT9, and RT10 samples

returns a valid 0)

To locate the start bit, data recovery does an asynchronous search for a 0 preceded by three 1s. When

the falling edge of a possible start bit occurs, the RT clock begins to count to 16.

Figure 18-6. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes samples at RT3, RT5, and RT7.

Table 18-2 summarizes the results of the start bit verification samples.

Table 18-2. Start Bit Verification

RT3, RT5, and RT7 Samples

Start Bit

Verification

Noise Flag

000

Yes

001

Yes

010

Yes

011

100

Yes

RT CLOCK

RESET

START BIT

QUALIFICATION

START BIT

VERIFICATION

DATA

SAMPLING

SAMPLES

CLOCK

RT CLOCK

STATE

START BIT

LSB

PE1/RxD

MC68HC908GR4MP Datasheet(PDF) 169 Page - Freescale Semiconductor, Inc

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